Patents Examined by Patricia D Reddington
  • Patent number: 10961115
    Abstract: A semiconductor structure includes a first substrate; a heater surrounded by the first substrate; a pressure adjusting material disposed over the first substrate and adjacent to the heater; a second substrate disposed over the first substrate; and a cavity enclosed by the first substrate and the second substrate, wherein the pressure adjusting material is disposed within the cavity.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Kuei-Sung Chang
  • Patent number: 10950664
    Abstract: A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 10950663
    Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: March 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hernan A. Castro, Stephen H. Tang, Stephen W. Russell
  • Patent number: 10950723
    Abstract: In a semiconductor device with a wide gap semiconductor, a gate insulating film is made of a material having a barrier against a minor carrier in an n-type body layer and having no barrier against a minor carrier in a p-type drift layer. As a result, in the semiconductor device with the wide gap semiconductor, a reduction in a conduction loss can be achieved while realizing an improvement in blocking resistance and securing reliability of the gate insulating film.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: March 16, 2021
    Assignee: DENSO CORPORATION
    Inventor: Kazuhiro Oyama
  • Patent number: 10937990
    Abstract: The present application relates to an encapsulation film, a method of manufacturing the same, an organic electronic device including the same, and a method of manufacturing the organic electronic device using the same. The present application provides an encapsulation film which can be formed to have a structure in which moisture or oxygen flowing from the outside into an organic electronic device can be effectively blocked, has excellent handling properties and processability, and also has excellent bonding properties with an organic electronic element and durability.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: March 2, 2021
    Assignee: LG CHEM LTD.
    Inventors: Hyun Jee Yoo, Hyun Suk Kim, Jung Ok Moon, Se Woo Yang, Jae Jin Kim, Dae Han Seo, Min Soo Song, Jung Woo Lee
  • Patent number: 10937862
    Abstract: Parasitic transistor formation under a semiconductor containing nanosheet device is eliminated by forming an airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate. The airgap is created by forming a sacrificial germanium-containing semiconductor material at the bottom of the source/drain regions prior to the epitaxial growth of the source/drain regions from physically exposed sidewalls of each semiconductor channel material nanosheet of a nanosheet material stack. After inner dielectric spacer formation, the sacrificial germanium-containing semiconductor material can be reflown to seal any possible openings to the semiconductor substrate. The source/drain regions are then epitaxially grown and thereafter, the sacrificial germanium-containing semiconductor material is removed from the structure creating the airgap between the source/drain regions of the semiconductor containing nanosheet device and the semiconductor substrate.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: March 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Choonghyun Lee, Xin Miao, Jingyun Zhang
  • Patent number: 10937861
    Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 2, 2021
    Assignee: Tessera, Inc.
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty
  • Patent number: 10923646
    Abstract: Superconducting switch having a persistent and a non-persistent state and its use as a driver in a memory system are described. An example superconducting switch includes a first superconducting layer and a second superconducting layer. The superconducting switch includes a first magnetic layer having a fixed magnetization state. The superconducting switch includes a second magnetic layer capable of being at least in a first or a second magnetization state. The superconducting switch is capable of being in a first state or a second state, and the superconducting switch is configured such that an application of a magnetic field to the second magnetic layer changes a magnetization of the second magnetic layer from the first magnetization state to the second magnetization state placing the superconducting switch in the second state and a removal of the magnetic field automatically returns the superconducting switch from the second state to the first state.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: February 16, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ian M. Dayton, Eric C. Gingrich
  • Patent number: 10916725
    Abstract: An organic light-emitting diode display panel, a method for fabricating the same and a display device are provided. The display panel is divided into a visible area and a non-display area, and includes: a base substrate, a plurality of organic light-emitting diode elements on the base substrate, an encapsulation layer on sides of the organic light-emitting diode elements away from the base substrate, a touch electrode layer on the side of the encapsulation layer away from the organic light-emitting diode elements, a peripheral circuit on the touch electrode layer away from the encapsulation layer, a circular polarizer on the sides of the touch electrode layer and the peripheral circuit away from the encapsulation layer, and an adhesive layer between the touch electrode layer and the circular polarizer.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: February 9, 2021
    Assignee: Chengdu BOE Optoelectronics Technology Co., Ltd.
    Inventors: Ping Wen, Ge Wang, Erjin Zhao, Jiang Xie, Zhiliang Jiang
  • Patent number: 10910583
    Abstract: An organic light-emitting diode includes a first electrode and a second electrode that face each other, an organic emission layer between the first electrode and the second electrode, and an inorganic hole injection layer between the first electrode and the organic emission layer. The inorganic hole injection layer includes oxide of a form A-B-O, including an element A and an element B. The element A is one of molybdenum (Mo) and tungsten (W). The element B is one of vanadium (V), niobium (Nb), and tantalum (Ta). An atom content (x) of the element B is greater than 0 and no more than 15 at % (0<x?15 at %) based on a total atom content of the inorganic hole injection layer.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyuneok Shin, Hongsick Park, Gyungmin Baek, Juhyun Lee, Sangwon Shin
  • Patent number: 10910521
    Abstract: A semiconductor light emitting device includes: a light emitting part for emitting ultraviolet light; and a coating part that coats an extraction surface from which the ultraviolet light emitted by the light emitting part is extracted. The coating part includes a resin matrix having a refractive index lower than a refractive index of an inorganic material forming the extraction surface and a hollow part that lowers a refractive index of the coating part as a whole by being dispersed in the resin matrix. The hollow part has an average particle diameter smaller than a peak wavelength of the ultraviolet light emitted by the light emitting part.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: February 2, 2021
    Assignee: NIKKISO CO., LTD.
    Inventor: Hideki Asano
  • Patent number: 10903272
    Abstract: A memory device may include a substrate having conductivity regions and a channel region. A first voltage line may be arranged over the channel region. A second voltage line, and third and fourth voltage lines may be electrically coupled to a first conductivity region and a second conductivity region respectively. Resistive units may be arranged between the third and fourth voltage lines and the second conductivity region. In use, changes in voltages applied between the second and third voltage lines, and between the second and fourth voltage lines may cause resistances of first and second resistive units to switch between lower and higher resistance values. The lower resistance value of the first resistive unit may be different from the lower resistance value of the second resistive unit and/or the higher resistance value of the first resistive unit may be different from the higher resistance value of the second resistive unit.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 26, 2021
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Lanxiang Wang, Shyue Seng Tan, Eng Huat Toh
  • Patent number: 10892106
    Abstract: An electronic device, such as, without limitation, a perovskite solar cell or a light emitting diode, includes an assembly including at least one electronic portion or component, and a composite coating layer covering at least part of the assembly including the at least one electronic portion or component. The composite coating layer includes a polymer material, such as, without limitation, PMMA or PMMA-PU, having nanoparticles, such as, without limitation, reduced graphene oxide or SiO2, embedded therein. The electronic device may further include a second coating layer including a second polymer material (such as, without limitation, PMMA or PMMA-PU without nanoparticles) positioned between the coating layer and the assembly.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: January 12, 2021
    Assignees: University of Pittsburgh—Of the Commonwealth System of Higher Education, Global Frontier Center for Multiscale Energy Systems
    Inventors: Jung-Kun Lee, Gillsang Han
  • Patent number: 10892445
    Abstract: An organic light emitting diode (OLED) lighting apparatus capable of improving lighting efficiency and lifetime by maximizing a light emitting area is disclosed. The OLED lighting apparatus may include a first electrode, which is provided with an embossing pattern at an interface at which the first electrode contacts an overcoat layer on a substrate. The first electrode may be made of a high refractive transparent conductive material, and may be arranged in an entire active area of the OLED lighting apparatus. The OLED lighting apparatus can improve light extraction efficiency through a light scattering due to a microlens effect through the first electrode provided with the embossing pattern, which facilitates elimination of a light extraction layer arranged at the interface between the substrate and the overcoat layer, thereby reducing a process yield and manufacturing cost.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: January 12, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jongmin Kim, Taejoon Song
  • Patent number: 10892389
    Abstract: The present application relates to a packaging leadframe and a packaging structure. The packaging leadframe includes a substrate layer and a sidewall structure. A surface of the substrate layer is provided with at least one metal bump structure, a circuit layer also is laid on the surface of the substrate layer and can be electrically coupled with a LED chip. The sidewall structure is disposed on the surface with the metal bump structure, and includes a halocarbon polymer matrix and a plurality of light reflective particles uniformly mixed together. The halocarbon polymer may be poly tetra fluoroethylene or polyvinylidene fluoride. In this regard, the packaging leadframe has high reflectivity to ultraviolet light and good resistance to ultraviolet radiation.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: January 12, 2021
    Assignee: KAISTAR LIGHTING (XIAMEN) CO., LTD.
    Inventor: Guoheng Qin
  • Patent number: 10886465
    Abstract: A memory cell includes: a first contact feature partially embedded in a first dielectric layer; a barrier layer, lining the first contact feature, that comprises a first portion disposed between the first contact feature and first dielectric layer, and a second portion disposed above the first dielectric layer; a resistive material layer disposed above the first contact feature, the resistive material layer coupled to the first contact feature through the second portion of the barrier layer; and a second contact feature embedded in a second dielectric layer above the first dielectric layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huei-Tsz Wang, Po-Shu Wang, Wei-Ming Wang
  • Patent number: 10861925
    Abstract: A display apparatus includes a substrate having a display area and a peripheral area, wirings over the peripheral area that extend in a first through third areas, an interval between the wirings in the second area is greater than an interval between the wirings in each of the first and third areas, an insulating layer covering the wirings and having a first uneven surface corresponding to the wirings, a first conductive layer over the insulating layer and including a second uneven surface corresponding to the first uneven surface, a flat planarization layer over the first conductive layer and exposing at least a portion of the first conductive layer, a second conductive layer electrically connected to the first conductive layer, at least a portion of the second conductive layer is over the planarization layer, and a polarization plate on the second conductive layer.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Joongsoo Moon, Kwangmin Kim, Yangwan Kim, Cheolgon Lee, Youngjin Cho, Changkyu Jin
  • Patent number: 10861793
    Abstract: Aspects generally relate to tuning a guard ring in an integrated circuit. A guard ring with a gap surrounds a circuit. The level of isolation provided by the guard ring at a particular frequency can be adjusted by coupling a tuning circuit cross the gap of the guard ring. If the circuit in the guard ring is an inductive circuit the level of inductance at a particular frequency can be adjusted by selecting the appropriate tuning circuit across the gap of the guard ring.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 8, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Ye Lu, Chao Song
  • Patent number: 10854787
    Abstract: A component having a boundary element is disclosed. In an embodiment a component comprises a semiconductor chip, a housing and a reflective layer, wherein the housing has a shaped body and a base body, the shaped body laterally enclosing the base body at least in places and being different from the reflective layer. In a plan view, the base body has a free area which is uncovered by the shaped body. The free area or a bottom surface of a cavity comprises a mounting surface for the semiconductor chip, wherein the semiconductor chip is arranged on the mounting surface. The bottom surface or the free area is partially covered by the reflective layer, wherein the mounting surface is enclosed at least in regions by a boundary element which adjoins the reflective layer and is configured to prevent the semiconductor chip from being covered by the reflective layer.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: December 1, 2020
    Assignee: OSAM OLED GMBH
    Inventors: Teik Yee Wong, Chee Weng Soong, Rajah Prakash, Christian Betthausen, Chee-Eng Ooi, Ismail Ithnain, Choo Kean Lim, Weng Heng Chan
  • Patent number: 10847505
    Abstract: A semiconductor package includes a first die; a first redistribution structure over the first die, the first redistribution structure being conterminous with the first die; a second die over the first die, a first portion of the first die extending beyond a lateral extent of the second die; a conductive pillar over the first portion of the first die and laterally adjacent to the second die, the conductive pillar electrically coupled to first die; a molding material around the first die, the second die, and the conductive pillar; and a second redistribution structure over the molding material, the second redistribution structure electrically coupled to the conductive pillar and the second die.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: November 24, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chia Lai, Kuo Lung Pan, Hung-Yi Kuo, Tin-Hao Kuo, Hao-Yi Tsai, Chung-Shi Liu, Chen-Hua Yu