Abstract: It is highly desirable in electronic systems to conserve space on printed circuit boards (PCB). This disclosure describes voltage regulation in electronic systems, and more specifically to integrating voltage regulators and associated passive components into semiconductor packages with at least a portion of the circuits whose voltage(s) they are regulating.

Abstract: A semiconductor device includes a heat sink, a semiconductor chip and a circuit board that are fixed to the heat sink with a fixing material, plural leads connected to the semiconductor chip and the circuit board via wires, and mold resin provided on the heat sink. The mold resin covers parts of the leads, the wires, and the semiconductor chip, and exposes remainders of the leads. The surfaces of the leads and the heat sink are provided with roughened plating having a surface roughness RMS=150 nm or more. The fixing material is solder or sintered silver. The water absorption rate of the mold resin is 0.24% or less.

Abstract: The semiconductor structure includes a plurality of FETs disposed on a semiconductor substrate, the FETs including gates with elongated shape oriented in a first direction; a first metal layer of first metal lines disposed over the gates and oriented in a second direction perpendicular to the first direction; a second metal layer of second metal lines disposed over the first metal layer and oriented in the first direction; and a third metal layer of third metal lines oriented in the second direction and disposed over the second metal layer. The first metal lines have a first pitch P1; the second metal lines have a second pitch P2; the third metal lines have a third pitch P3; and the gates have a fourth pitch P4, wherein a ratio of the second pitch over the fourth pitch P2:P4 is about 3:2.

Abstract: A semiconductor device includes a heat sink, a semiconductor chip and a circuit board that are fixed to the heat sink with a fixing material, plural leads connected to the semiconductor chip and the circuit board via wires, and mold resin provided on the heat sink. The mold resin covers parts of the leads, the wires, and the semiconductor chip, and exposes remainders of the leads. The surfaces of the leads and the heat sink are provided with roughened plating having a surface roughness RMS=150 nm or more. The fixing material is solder or sintered silver. The water absorption rate of the mold resin is 0.24% or less.

Abstract: A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.

Abstract: A method comprises forming a plurality of interconnect structures including a dielectric layer, a metal line and a redistribution line over a carrier, attaching a semiconductor die on a first side of the plurality of interconnect structures, forming an underfill layer between the semiconductor die and the plurality of interconnect structures, mounting a top package on the first side the plurality of interconnect structures, wherein the top package comprises a plurality of conductive bumps, forming an encapsulation layer over the first side of the plurality of interconnect structures, wherein the top package is embedded in the encapsulation layer, detaching the carrier from the plurality of interconnect structures and mounting a plurality of bumps on a second side of the plurality of interconnect structures.

Abstract: A method for making a memory device, includes: forming a first dielectric layer over a bottom electrode; forming a first void extending through the first dielectric layer to expose a portion of an upper boundary of the bottom electrode; forming a first conductive structure lining along respective sidewalls of the first void and the exposed portion of the upper boundary of the bottom electrode; filling the first void with the first dielectric layer; and forming a phase change material layer over the first dielectric layer to cause the phase change material layer to contact at least a portion of a sidewall of the first conductive structure.

Abstract: A vertical IGBT device is disclosed. The vertical IGBT structure includes an active MOSFET cell array formed in an active region at a front side of a semiconductor substrate of a first conductivity type. One or more column structures of a second conductivity type concentrically surround the active MOSFET cell array. Each column structure includes a column trench and a deep column region. The deep column region is formed by implanting implants of the second conductivity type into the semiconductor substrate through the floor of the column trench. Dielectric side wall spacers are formed on the trench side walls except a bottom wall of the trench and the column trench is filled with poly silicon of the second conductivity type. One or more column structures are substantially deeper than the active MOSFET cell array.

Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

Abstract: An integrated circuit (IC) provides high performance and high functional density. A first back-end-of-line (BEOL) interconnect structure and a second BEOL interconnect structure are respectively under and over a semiconductor substrate. A first electronic device and a second electronic device are between the semiconductor substrate and respectively a bottom of the first BEOL interconnect structure and a top of the second BEOL interconnect structure. A through substrate via (TSV) extends through the semiconductor substrate, from the first BEOL interconnect structure to the second BEOL interconnect structure. A method for manufacturing the IC is also provided.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a semiconductor substrate having a first pair of sidewalls extending in a first direction and a second pair of sidewalls. One or more of the second pair of sidewalls extend past the first pair of sidewalls in a second direction that intersects the first direction as viewed from a top-view of the semiconductor substrate. The first pair of sidewalls and the second pair of sidewalls define one or more trenches within the semiconductor substrate. An interconnecting structure including a conductive material is disposed within the one or more trenches in the semiconductor substrate. The interconnecting structure continuously extends completely through the semiconductor substrate.

Abstract: In a method for manufacturing an organic EL display panel including: preparing a substrate; forming pixel electrodes in a matrix of rows and columns; forming banks extending in a column direction at least between the pixel electrodes in a row direction; forming a first light emitting layer by applying an ink including a light emitting material in a first gap selected from a plurality of gaps between the banks; forming a second light emitting layer by a vapor deposition method to be continuous above both the first light emitting layer and the pixel electrodes in a second gap adjacent in the row direction to the first gap; and forming a counter electrode above the second light emitting layer, a height of portions of the banks adjacent to the second gap is made to be greater than a height of portions of the banks adjacent to the first gap.

Abstract: The present disclosure provides methods for forming conductive features in a dielectric layer without using adhesion layers or barrier layers and devices formed thereby. In some embodiments, a structure comprising a dielectric layer over a substrate, and a conductive feature disposed through the dielectric layer. The dielectric layer has a lower surface near the substrate and a top surface distal from the substrate. The conductive feature is in direct contact with the dielectric layer, and the dielectric layer comprises an implant species. A concentration of the implant species in the dielectric layer has a peak concentration proximate the top surface of the dielectric layer, and the concentration of the implant species decreases from the peak concentration in a direction towards the lower surface of the dielectric layer.

Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a circuit layer over the substrate. The semiconductor device further includes a test line on the circuit layer. The semiconductor device further includes a capacitor on the substrate. The capacitor includes a first conductor, wherein the first conductor is on a portion of the substrate exposed by the circuit layer; a second conductor; and an insulator between the first conductor and the second conductor, wherein the insulator surrounds the first conductor and the second conductor.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a conductive element disposed within a dielectric structure over the substrate. The conductive element has a top surface extend between outermost sidewalls of the conductive element. A first resistive random access memory (RRAM) element is arranged within the dielectric structure and has a first data storage layer directly contacting the top surface of the conductive element. A second RRAM element is arranged within the dielectric structure and has a second data storage layer directly contacting the top surface of the conductive element.

Abstract: Embodiments relate to sensor and sensing devices, systems and methods. In an embodiment, a micro-electromechanical system (MEMS) device comprises at least one sensor element; a framing element disposed around the at least one sensor element; at least one port defined by the framing element, the at least one port configured to expose at least a portion of the at least one sensor element to an ambient environment; and a thin layer disposed in the at least one port.

Abstract: A method of forming a transistor device is provided. The method includes forming a plurality of gate structures including a gate spacer and a gate electrode on a substrate, wherein the plurality of gate structures are separated from each other by a source/drain contact. The method further includes reducing the height of the gate electrodes to form gate troughs, and forming a gate liner on the gate electrodes and gate spacers. The method further includes forming a gate cap on the gate liner, and reducing the height of the source/drain contacts between the gate structures to form a source/drain trough. The method further includes forming a source/drain liner on the source/drain contacts and gate spacers, wherein the source/drain liner is selectively etchable relative to the gate liner, and forming a source/drain cap on the source/drain liner.

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

Abstract: The invention provides a manufacturing method of a heat dissipation component. A substrate is provided. The substrate has an outer surface. A patterned dry film is formed on the outer surface. The patterned dry film is composed of a plurality of microporous patterns. A thermally conductive layer is formed on a region excluding the microporous patterns on the outer surface. The patterned dry film is removed to form a plurality of micro meshes. The thermally conductive layer surrounds the micro meshes.