Abstract: An integrated circuit device includes a first insulation layer on a substrate, a lower wiring structure in the first insulation layer and including a metal layer and a conductive barrier layer, such that the metal layer is on the conductive barrier layer, an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness, a capping layer overlapping a portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness, a second insulation layer overlapping the etch stop layer and the capping layer, and an upper wiring structure connected to another portion of the upper surface of the metal layer not overlapped by the capping layer in the second insulation layer.

Abstract: A light emitting device includes: a base member having a first surface including a first region and a second region; a first frame surrounding the first region on the base member; a light emitting element provided on the first region; a light-transmissive first member provided inward of the first frame, and covering the light emitting element; a second frame surrounding the second region; an electronic component provided in the second region; and a non-light-transmissive second member provided inward of the second frame, and covering the electronic component. A part of the first frame and a part of the second frame are integrated with each other. An upper surface of the first member is positioned higher than upper surfaces of the first frame, the second frame, and the second member.

Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.

Abstract: A semiconductor structure includes a semiconductor substrate and a multi-layer patterning material film stack formed on the semiconductor substrate. The patterning material film stack includes a resist layer formed over one or more additional layers. The semiconductor structure further includes a metal-containing top coat formed over the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.

Abstract: A semiconductor device for attaching to a flexible display is provided. The semiconductor device includes a substrate including semiconductive material, and a conductive pad disposed on the substrate. Each corner of the conductive pad is free of right angle. The flexible display includes a flexible substrate including a circuit, and the semiconductor device. A method of manufacturing a flexible display includes providing a substrate including semiconductive material, and forming a conductive pad on the substrate, wherein each corner of the conductive pad is free of right angle. The method further includes providing a flexible substrate, and bonding the conductive pad to a conductor of a circuit of the flexible substrate.

Abstract: The present disclosure provides a thin film transistor, including a base substrate, an active layer and a source/drain, and a conductive layer. The active layer and an outer edge of the conductive layer are formed in the same etching process. The present disclosure further provides a method for manufacturing a thin film transistor, including forming an active material layer and a conductive material layer, forming a photoresist on the conductive material layer, exposing and developing the photoresist by means of a halftone mask, removing segments of the active material layer and the conductive material layer corresponding to a photoresist completely-removed region by a same etching process, partially removing the photoresist in a photoresist completely-retained region and completely removing the photoresist in a photoresist partially-retained region, and removing a segment of the conductive material layer corresponding to the photoresist partially-retained region.

Abstract: An organic light emitting diode display device includes a substrate having a plurality of subpixels which each have an emission region and a non-emission region defined along an edge of the emission region. A reflective barrier is disposed to correspond to the non-emission region and includes a reflective side surface. An overcoat layer is disposed on an upper portion of the reflective barrier. A light emitting diode includes a first electrode, an organic light emitting layer, and a second electrode, which are sequentially disposed on the overcoat layer. The reflective side surface of the reflective barrier is inversely tapered such that a width thereof is decreased in a traveling direction of light emitted from the organic light emitting layer.

Abstract: A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first semiconducting layer, a second fin formed in a second semiconductor layer, and an insulating layer disposed between the first fin and the second fin. The first fin, the second fin, and the insulating layer form a stacked structure above a substrate. Sidewalls of the first fin are substantially more vertical than sidewalls of the second fin.

Abstract: Provided is a monitoring apparatus including an acquisition unit that acquires first time-series data which is time-series data of a measured value and/or a feature amount regarding an electrical device group, and a registration and updating unit that, when a difference in values between a pre-state-change data value which is any one of a data value at a first point in time in the first time-series data and a statistic of a plurality of data values from a point in time earlier than the first point in time by a predetermined period of time to the first point in time and a post-state-change data value which is any one of a data value at a second point in time later than the first point in time and a statistic of a plurality of data values from the second point in time to a point in time later than the second point in time by a predetermined period of time satisfies a predetermined condition, stores a feature amount extracted from any waveform data of a total current consumption, a total power consumption, and a

Abstract: Described are microelectronic devices including a substrate formed with multiple build-up layers, and having at least one build-up layer formed of a fiber-containing material. A substrate can include a buildup layers surrounding an embedded die, or outward of the build-up layer surrounding the embedded die that includes a fiber-containing dielectric. Multiple build-up layers located inward from a layer formed of a fiber-containing dielectric will be formed of a fiber-free dielectric.

Abstract: A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the device. The method further includes forming a heat sink in at least one of the plurality of insulator layers and proximate to the device. The heat sink includes a reservoir of phase change material having a melting point temperature that is less than an upper limit of a design operating temperature of the chip.

Abstract: In a general aspect, a semiconductor device assembly can include a semiconductor die having a first surface including active circuitry, a second surface opposite the first surface, and a plurality of side surfaces. Each of the plurality of side surfaces can extend between the first surface of the semiconductor die and the second surface of the semiconductor die. The semiconductor device assembly can also include a conductive spacer having a cavity defined therein. The semiconductor die can be electrically and thermally coupled with the conductive spacer, the semiconductor die being at least partially embedded in the cavity.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first resistive element and a second resistive element over the semiconductor substrate. The semiconductor device structure also includes a first conductive feature electrically connected to the first resistive element and a second conductive feature electrically connected to the second resistive element. The semiconductor device structure further includes a dielectric layer surrounding the first conductive feature and the second conductive feature.

Abstract: The systems and methods provided herein relate to extracting maturity-based properties from input log data obtained by a downhole well logging tool. A maturity inversion is performed using the input log data, a log response model, and at least one maturity model to extract maturity-based properties from the input log data. The maturity-based properties are provided in an output log, such that subsequent down hole operation of the formation may account for the maturity-based properties.

Abstract: A semiconductor package structure including an encapsulating layer, a package substrate, and a conductive shielding layer is provided. The package substrate has a device region covered by the encapsulating layer and an edge region surrounding the device region and exposed from the encapsulating layer. The package substrate includes an insulating layer and a patterned conductive layer in a level of the insulating layer. The patterned conductive layer includes conductors in and along the edge region. The edge region is partially exposed from the conductors, as viewed from a top-view perspective. The conductive shielding layer covers and surrounds the encapsulating layer and is electrically connected to the conductors.

Abstract: A semiconductor structure includes a first substrate; a heater surrounded by the first substrate; a pressure adjusting material disposed over the first substrate and adjacent to the heater; a second substrate disposed over the first substrate; and a cavity enclosed by the first substrate and the second substrate, wherein the pressure adjusting material is disposed within the cavity.

Abstract: A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

Abstract: In a semiconductor device with a wide gap semiconductor, a gate insulating film is made of a material having a barrier against a minor carrier in an n-type body layer and having no barrier against a minor carrier in a p-type drift layer. As a result, in the semiconductor device with the wide gap semiconductor, a reduction in a conduction loss can be achieved while realizing an improvement in blocking resistance and securing reliability of the gate insulating film.

Abstract: Methods and apparatuses for a cross-point memory array and related fabrication techniques are described. The fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. Each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. The fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3D memory array within the composite stack while using a reduced number of processing steps. The fabrication techniques may also be suitable for forming a socket region where the 3D memory array may be coupled with other components of a memory device.

Abstract: A method of forming a semiconductor structure includes forming a first middle-of-line (MOL) oxide layer and a second MOL oxide layer in the semiconductor structure. The first MOL oxide layer including multiple gate stacks formed on a substrate, and each gate stack of the gate stacks including a source/drain junction. A first nitride layer is formed over a silicide in the first MOL oxide layer. A second nitride layer is formed. Trenches are formed through the second nitride layer down to the source/drain junctions. A nitride cap of the plurality of gate stacks is selectively recessed. At least one self-aligned contact area (CA) element is formed within the first nitride layer. The first MOL oxide layer is selectively recessed. An air-gap oxide layer is deposited. The air gap oxide layer is reduced to the at least one self-aligned CA element and the first nitride layer.