Abstract: A semiconductor device is provided comprising a semiconductor substrate of a first conductivity type and a dummy trench portion having a main body portion and one or more branch portions, the main body portion formed in a front surface of the semiconductor substrate and extending in a predetermined extending direction, the branch portions extending from the main body portion in directions different from the extending direction. The semiconductor substrate has an emitter region of first conductivity type and a base region of a second conductivity type which are provided sequentially from the front surface side of the semiconductor substrate, and the dummy trench portion has a dummy trench which penetrates the emitter region and the base region from the front surface of the semiconductor substrate, and a dummy insulating portion which is provided within the dummy trench.

Abstract: A method of producing an optoelectronic component includes providing a carrier, generating a plurality of recesses in the carrier, applying a plurality of drops of a cover material to the carrier, introducing an optoelectronic semiconductor chip including a semiconductor body and contact elements on an underside of the semiconductor body into at least some of the drops, and curing the drops of the cover material into cover bodies, wherein at least some of the drops are completely surrounded by recesses in the carrier, and the recesses in the carrier are a stop edge for the cover material during introduction of the optoelectronic semiconductor chip.

Abstract: A semiconductor memory device includes a separation member defining active regions of a substrate. Gate lines intersect the active regions and are each buried in a trench formed in the substrate. Each of the gate lines includes a lower electrode structure and an upper electrode structure on the lower electrode structure. The upper electrode structure includes a source layer substantially covering a sidewall of the trench and including a work-function adjustment element. A conductive layer is on the source layer. A work-function adjustment layer is disposed between the source layer and the conductive layer. The work-function adjustment layer includes a material different from that of the source layer and is doped with the work-function adjustment element.

Abstract: A pixel definition layer, a manufacturing method thereof, a display substrate and a display device are provided. The pixel definition layer includes: a lyophilic material layer on a base substrate, and a lyophobic material layer on the side, away from the base substrate, of the lyophilic material layer. The pixel definition layer defines a plurality of pixel regions, in an arrangement of array, on the base substrate, each pixel region comprises at least two sub-pixel regions, and the lyophilic material layers that define the different sub-pixel regions in the same pixel region have different thicknesses. With the pixel definition layer, the climbing quantities of the different solutions in the corresponding pixel definition layers are the same as much as possible. The film-forming uniformity of the solutions in the pixel region is effectively improved.

Abstract: A method of fabricating a semiconductor structure includes forming an alignment mark layer on a substrate; patterning the alignment mark layer for forming at least one alignment mark feature; forming a bottom conductive layer on the patterned alignment mark layer in a substantially conformal manner; forming an insulator layer on the bottom conductive layer; and forming a top conductive layer on the insulator layer.

Abstract: A semiconductor memory device disposed over a substrate includes a common electrode, a selector material layer surrounding the common electrode, and a plurality of phase change material layers in contact with the selector material layer.

Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.

Abstract: An integrated circuit (IC) may include an active device layer on a front-side surface of a semiconductor device substrate. The IC may also include a front-side dielectric layer having a first surface opposite a second surface, the first surface contacting the active device layer. The IC may further include a porous semiconductor handle substrate contacting the second surface of the front-side dielectric layer. The porous semiconductor handle substrate may be uniformly doped.

Abstract: A semiconductor device includes a semiconductor layer and a metal electrode. The metal electrode is provided on the semiconductor layer. The metal electrode includes first to third metal regions. The first metal region contacts the semiconductor layer and includes a first metal element as a main component. The second metal region is provided on the first metal region and includes a second metal element as a main component. The third metal region is provided on the second metal region. The third metal region has a thickness in a first direction directed from the semiconductor layer toward the second metal region. The thickness of the third metal region is larger than a total thickness in the first direction of the first metal region and the second metal region. The second metal element has a standard free energy of oxide generation larger than that of the first metal element.

Abstract: A three-dimensional (3D) semiconductor memory device includes a source structure disposed on a horizontal semiconductor layer and including a first source conductive pattern and a second source conductive pattern which are sequentially stacked on the horizontal semiconductor layer, an electrode structure including a plurality of electrodes vertically stacked on the source structure, and a vertical semiconductor pattern penetrating the electrode structure and the source structure, wherein a portion of a sidewall of the vertical semiconductor pattern is in contact with the source structure. The first source conductive pattern includes a discontinuous interface at a level between a top surface of the horizontal semiconductor layer and a bottom surface of the second source conductive pattern.

Abstract: A multipart lid is provided. The multipart lid may include a formed upper lid designed for maximum heat dissipation, a coined lower lid joined to the formed upper lid, where the coined lower lid comprises a coefficient of thermal expansion (CTE) substantially equal to a CTE of a first semiconductor component. A structure is provided. The structure may include a substrate, a first semiconductor component electrically connected and mounted on the substrate, one or more discrete components electrically connected and mounted on the substrate, a substrate mounted multipart lid covering both the semiconductor component and the one or more discrete components, where the multipart lid comprises a heat dissipating upper lid and a lower lid, where a coefficient of thermal expansion (CTE) of the lower lid substantially matches a CTE of the first semiconductor component.

Abstract: A pixel structure includes a thin film transistor, a first insulating layer, a first transparent conductive layer, a second insulating layer, a connecting hole and a second transparent conductive layer. The thin film transistor is disposed on the substrate, and the thin film transistor includes a gate, a source and a drain. The first insulating layer, the first transparent conductive layer and the second insulating layer are disposed on the thin film transistor in sequence, and the first transparent conductive layer includes a pixel electrode. The connecting hole exposes a portion of the pixel electrode and a portion of the drain. The second transparent conductive layer is disposed on the second insulating layer, the second transparent conductive layer includes a common electrode and a connecting electrode electrically insulated to the common electrode, and the connecting electrode extends into the connecting hole.

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same are provided. A memory device may include a semiconductor layer including first and second regions, first vertical structures on the first region and extending in a first direction perpendicular to a top surface of the semiconductor layer, and second vertical structures on the second region and extending in the first direction. The first vertical structure may include a vertical semiconductor pattern extending in the first direction and in contact with the semiconductor layer, and a first data storage pattern surrounding the vertical semiconductor pattern. The second vertical structure may include an insulation structure extending in the first direction and in contact with the semiconductor layer, and a second data storage pattern surrounding the insulation structure.

Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an antenna region. The insulating encapsulation encapsulates the integrated circuit. The redistribution circuit structure is disposed on the integrated circuit and the insulating encapsulation. The redistribution circuit structure is electrically connected to the integrated circuit, and the redistribution circuit structure includes a redistribution region and a dummy region including a plurality of dummy patterns embedded therein, wherein the antenna region includes an inductor and a wiring-free dielectric portion, and the wiring-free dielectric portion of the antenna region is between the inductor and the dummy region.

Abstract: A light emitting diode device, an array substrate and a display device. The light emitting diode device includes a substrate, a first sub-light emitting unit disposed on the substrate, and a second sub-light emitting unit disposed on a side of the first sub-light emitting unit away from the substrate. The first sub-light emitting unit includes a first semiconductor layer of a first conductivity type, a first light emitting layer, and a second semiconductor layer of a second conductivity type which are each disposed successively in a direction away from the substrate. The second sub-light emitting unit includes the second semiconductor layer, a second light emitting layer, and a third semiconductor layer of the first conductivity type. Each layer is disposed successively in the direction away from the substrate. The first conductivity type is different from the second conductivity type.

Abstract: A method of forming a semiconductor structure includes forming a middle-of-line (MOL) oxide layer in the semiconductor structure. The MOL oxide layer including multiple gate stacks formed on a substrate. A nitride layer is formed over a silicide in the MOL oxide layer. At least one self-aligned contact area (CA) element is formed within the nitride layer. The MOL oxide layer is selectively recessed on a first side and a second side of the at least one self-aligned CA element leaving remaining portions of the MOL oxide layer on the nitride layer and a nitride. A nitride cap of the plurality of gate stacks is selectively recessed. An air-gap oxide layer is deposited for introducing one or more air-gaps in the deposited air-gap oxide layer. The air gap oxide layer is reduced to the at least one self-aligned CA element and the nitride layer.

Abstract: A magnetic component includes a semiconductor substrate, a first winding that is located in the semiconductor substrate and that includes at least two turns, and intra-winding insulation located between two adjacent turns of the at least two turns and including doped regions in the semiconductor substrate that define either an NPN-junction or a PNP junction.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate which includes a cell region including first and second regions, and a peri region more adjacent to the second region than adjacent to the first region, first and second lower electrodes disposed in the first and second regions, respectively, first and second lower support patterns disposed on outer walls of the first and second lower electrodes, respectively, an upper support pattern disposed on outer walls of the first and second lower electrodes, and being on and spaced apart from the first and second lower support patterns, a dielectric layer disposed on surfaces of the first and second lower electrodes, the first and second lower support patterns, and the upper support pattern, and an upper electrode disposed on a surface of the dielectric layer, wherein thickness of the first lower support pattern is smaller than thickness of the second lower support pattern.

Abstract: An inkjet printing OLED display panel and manufacturing method are provided. The method includes sequentially forming a passivation layer and a planarization layer on thin-film transistors on a glass substrate, and the passivation layer covers the thin-film transistors; forming vias both at the passivation layer and the planarization layer; forming anodes on the planarization layer, and the anodes are electrically connected to the thin-film transistors through the vias; depositing a pixel definition layer on the planarization layer, and the pixel definition layer covers the anodes; using a half-tone mask to define a pattern of the pixel definition layer such that a region of the pixel definition layer located above the anodes forms a notch, and a height of the pixel definition layer located between the anodes is decreased; using an inkjet printing technology to form a light-emitting layer in the notch of the pixel definition layer.