Patents Examined by Patricia D Reddington
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Patent number: 11177384Abstract: A method of making a semiconductor device includes depositing an isolation region between adjacent fins of a plurality of fins over a substrate, wherein a top-most surface of the isolation region is a first distance from a bottom of the substrate. The method further includes doping each of the plurality of fins with a first dopant having a first dopant type to define a first doped region in each of the plurality of fins, wherein a bottom-most surface of the first doped region is a second distance from the bottom of the substrate, and the second distance is greater than the first distance. The method further includes doping each of the plurality of fins with a second dopant having a second dopant type to define a second doped region in each of the plurality of fins, wherein the second doped region contacts the isolation region.Type: GrantFiled: January 28, 2020Date of Patent: November 16, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chewn-Pu Jou, Tzu-Jin Yeh, Chia-Chung Chen
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Patent number: 11177130Abstract: A lithographic patterning method includes forming a multi-layer patterning material film stack on a semiconductor substrate, the patterning material film stack including a resist layer formed over one or more additional layers, and forming a metal-containing top coat over the resist layer. The method further includes exposing the multi-layer patterning material film stack to patterning radiation through the metal-containing top coat to form a desired pattern in the resist layer, removing the metal-containing top coat, developing the pattern formed in the resist layer, etching at least one underlying layer in accordance with the developed pattern, and removing remaining portions of the resist layer. The metal-containing top coat can be formed, for example, by atomic layer deposition or spin-on deposition over the resist layer, or by self-segregation from the resist layer.Type: GrantFiled: May 6, 2019Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Ekmini Anuja De Silva, Dario Goldfarb, Nelson Felix, Daniel Corliss, Rudy J. Wojtecki
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Patent number: 11171221Abstract: Techniques for forming VFET bottom source and drain epitaxy with anchors are provided. In one aspect, a method of forming a VFET device includes: patterning at least one fin in a substrate; forming anchors on opposite ends of the at least one fin; laterally etching a base of the at least one fin, wherein the anchors prevent the lateral etching from being performed on the ends of the at least one fin; forming bottom source and drains at the base of the at least one fin between the anchors; removing the anchors; forming bottom spacers on the bottom source and drains; forming gates above the bottom spacers alongside the at least one fin; forming top spacers above the gates; and forming top source and drains above the top spacers at a top of the at least one fin. VFET devices are also provided.Type: GrantFiled: June 24, 2019Date of Patent: November 9, 2021Assignee: International Business Machines CorporationInventors: Chen Zhang, Tenko Yamashita
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Patent number: 11164827Abstract: An electronic circuit including a substrate having a first dielectric characteristic. The substrate can include a first side and a second side. An intermediary material can be disposed within the substrate. For instance, the intermediary material can be located between the first side and the second side. The intermediary material can include a second dielectric characteristic, where the second dielectric characteristic is different than the first dielectric characteristic. A first conductive layer can be disposed on the first side, and a second conductive layer can be disposed on the second side. A conductive path can be electrically coupled between the first conductive layer and the second conductive layer. The conductive path can be in contact with at least a portion of the intermediary material.Type: GrantFiled: December 19, 2017Date of Patent: November 2, 2021Assignee: Intel CorporationInventors: Jackson Chung Peng Kong, Bok Eng Cheah, Ping Ping Ooi, Kooi Chi Ooi
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Patent number: 11158763Abstract: A dislocation-free GaN/InGaN-based nanowires-LED epitaxially grown on a transparent, electrically conductive template substrate. The simultaneous transparency and conductivity are provided by a thin, translucent metal contact integrated with a quartz substrate. The light transmission properties of the translucent metal contact are tunable during epitaxial growth of the nanowires LED. Transparent light emitting diodes (LED) devices, optical circuits, solar cells, touch screen displays, and integrated photonic circuits can be implemented using the current platform.Type: GrantFiled: April 2, 2020Date of Patent: October 26, 2021Assignee: KING ABDULLAH UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Boon S. Ooi, Aditya Prabaswara, Bilal Janjua, Tien Khee Ng
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Patent number: 11152495Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.Type: GrantFiled: September 30, 2019Date of Patent: October 19, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan B. Botula, Max L. Lifson, James A. Slinkman, Theodore G. Van Kessel, Randy L. Wolf
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Patent number: 11127892Abstract: A qubit coupling device includes: a dielectric substrate including a trench; a first superconductor layer on a surface of the dielectric substrate where an edge of the first superconductor layer extends along a first direction and at least a portion of the superconductor layer is in contact with the surface of the dielectric substrate, and where the superconductor layer is formed from a superconductor material exhibiting superconductor properties at or below a corresponding critical temperature; a length of the trench within the dielectric substrate is adjacent to and extends along an edge of the first superconductor layer in the first direction, and where the electric permittivity of the trench is less than the electric permittivity of the dielectric substrate.Type: GrantFiled: December 15, 2017Date of Patent: September 21, 2021Assignee: Google LLCInventor: Anthony Edward Megrant
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Patent number: 11127706Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.Type: GrantFiled: September 28, 2018Date of Patent: September 21, 2021Assignee: Intel CorporationInventors: Zhaozhi Li, Sanka Ganesan, Debendra Mallik, Gregory Perry, Kuan H. Lu, Omkar Karhade, Shawna M. Liff
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Patent number: 11119196Abstract: A time-of-flight (TOF) sensor includes a light source, a plurality of avalanche photodiodes, and a plurality of pulse generators. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, and the control circuitry includes logic that when executed by the control circuitry causes the time-of-flight sensor to perform operations. The operations include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. A plurality of pulses is output from the individual pulse generators corresponding to the individual avalanche photodiodes that received the light, and a timing signal is output when the plurality of pulses overlap temporally. A time is calculated when a first avalanche photodiode in the plurality of avalanche photodiodes received the light.Type: GrantFiled: October 25, 2019Date of Patent: September 14, 2021Assignee: OMNIVISION TECHNOLOGIES, INC.Inventor: Olivier Bulteel
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Patent number: 11121055Abstract: A semiconductor device module may include a leadframe spacer that provides the functions of both a leadframe and a spacer, while enabling a double-sided cooling configuration. Such a leadframe spacer may include a leadframe surface that provides a die attach pad (DAP) that is shared by at least two semiconductor devices. The leadframe spacer may include at least one downset, where the semiconductor devices may be attached within a recess defined by the at least one downset. A first substrate may be connected to a first side of the leadframe. A second substrate may be connected to downset surfaces of the at least one downset, and positioned for further connection to the semiconductor devices in a double-sided assembly.Type: GrantFiled: January 10, 2020Date of Patent: September 14, 2021Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Tzu-Hsuan Cheng, Yong Liu, Liangbiao Chen
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Patent number: 11114373Abstract: Semiconductor devices, integrated circuits and methods of forming the same are provided. In one embodiment, a semiconductor device includes a metal-insulator-metal structure which includes a bottom conductor plate layer including a first opening and a second opening, a first dielectric layer over the bottom conductor plate layer, a middle conductor plate layer over the first dielectric layer and including a third opening, a first dummy plate disposed within the third opening, and a fourth opening, a second dielectric layer over the middle conductor plate layer, and a top conductor plate layer over the second dielectric layer and including a fifth opening, a second dummy plate disposed within the fifth opening, a sixth opening, and a third dummy plate disposed within the sixth opening. The first opening, the first dummy plate, and the second dummy plate are vertically aligned.Type: GrantFiled: February 26, 2020Date of Patent: September 7, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yuan-Yang Hsiao, Hsiang-Ku Shen, Dian-Hau Chen
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Patent number: 11107877Abstract: An organic light emitting diode display includes: a substrate including a display area and a non-display area adjacent to the display area; a pixel thin film transistor positioned in the display area of the substrate; a first data wire positioned on the pixel thin film transistor; a second data wire positioned on the first data wire; an organic light emitting element positioned on the second data wire and electrically connected to the pixel thin film transistor through the first data wire and the second data wire; a circuit unit positioned in the non-display area of the substrate and including a circuit thin film transistor electrically connected to the pixel thin film transistor; and a common power supply line overlapping at least part of the circuit unit, electrically connected to the organic light emitting element, and formed on a same layer as the second data wire.Type: GrantFiled: October 25, 2018Date of Patent: August 31, 2021Assignee: Samsung Display Co., Ltd.Inventors: Kyong Tae Park, Sung Ho Cho, Seong Yeun Kang
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Patent number: 11094633Abstract: A microelectronic package bridge can comprising a plurality of ground layers, and a plurality of signal layers interwoven with the plurality of ground layers. Each of the signal layers can include a plurality of electrically conductive pathways. Each of the electrically conductive pathways can be arranged to form an electrical connection between one of a first plurality of bumps of a first die and one of a second plurality of bumps of a second die. Each of the plurality of electrically conductive pathways can have a length substantially equal to one another.Type: GrantFiled: June 30, 2016Date of Patent: August 17, 2021Assignee: Intel CorporationInventors: Zhiguo Qian, Kemal Aygun, Dae-Woo Kim, Jackie C. Preciado
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Patent number: 11081572Abstract: An approach for heat dissipation in integrated circuit devices is provided. A method includes forming an isolation layer on an electrically conductive feature of an integrated circuit device. The method also includes forming an electrically conductive layer on the isolation layer. The method additionally includes forming a plurality of nanowire structures on a surface of the electrically conductive layer.Type: GrantFiled: August 7, 2019Date of Patent: August 3, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Alan B. Botula, Max L. Lifson, James A. Slinkman, Theodore G. Van Kessel, Randy L. Wolf
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Patent number: 11081598Abstract: A trench MOS Schottky diode includes a first semiconductor layer including a Ga2O3-based single crystal, a second semiconductor layer that is a layer laminated on the first semiconductor layer and that includes a Ga2O3-based single crystal and a trench opened on a surface thereof opposite to the first semiconductor layer, an anode electrode formed on the surface of the second semiconductor layer, a cathode electrode formed on a surface of the first semiconductor layer, an insulating film covering an inner surface of the trench, and a trench MOS gate that is buried in the trench so as to be covered with the insulating film and is in contact with the anode electrode. The second semiconductor layer includes a lower layer on a side of the first semiconductor layer and an upper layer on a side of the anode electrode having a higher donor concentration than the lower layer.Type: GrantFiled: February 27, 2018Date of Patent: August 3, 2021Assignees: TAMURA CORPORATION, NOVEL CRYSTAL TECHNOLOGY, INC.Inventors: Kohei Sasaki, Masataka Higashiwaki
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Patent number: 11081398Abstract: A vertical fin field effect transistor includes a semiconductor fin disposed over a well region and a gate conductor layer disposed over a sidewall of the fin, and extending laterally over a top surface of the well region adjacent to the fin. The extension of the gate conductor over the bottom source/drain effectively increases the channel length of the vertical FinFET device independent of the fin height. A bottom source/drain region is laterally adjacent to the well region such that the portion of the well region covered by the laterally extended gate stack is between the bottom source/drain region and the portion of the well region immediately under the fin. A top source/drain region is located above the fin. The device is operated in circuits by use of electrical contacts to the bottom source/drain, the gate conductor, and the top source/drain.Type: GrantFiled: June 13, 2018Date of Patent: August 3, 2021Assignee: GLOBALEOUNDRIES U.S. INC.Inventors: Xusheng Wu, David Paul Brunco
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Patent number: 11075200Abstract: An integrated semiconductor device includes a substrate, a first vertical transistor, and a second vertical transistor. The substrate has a first substrate region and a second substrate region. The first vertical transistor is disposed on the substrate in the first substrate region. The first vertical transistor is n-type field-effect vertical transistor (n-VFET) with a first channel crystalline orientation. The second vertical transistor is disposed on the substrate in the second substrate region. The second vertical transistor is p-type field-effect vertical transistor (p-VFET) with a second channel crystalline orientation. The first channel crystalline orientation is different from the second channel orientation. A common bottom source and drain region as well as common bottom and top spacers regions are provided for the first vertical transistor and the second vertical transistor.Type: GrantFiled: November 22, 2019Date of Patent: July 27, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Zhenxing Bi, Kangguo Cheng, Zheng Xu, Dexin Kong
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Patent number: 11075108Abstract: The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.Type: GrantFiled: May 20, 2019Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Chun Hsiung Tsai, Yan-Ting Lin, Clement Hsingjen Wann
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Patent number: 11069620Abstract: A die interconnect substrate comprises a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate comprises a multilayer substrate structure comprising a substrate interconnect. The bridge die is embedded in the multilayer substrate structure. The substrate interconnect extends from a level above the bridge die to a level below the bridge die. The multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material. The multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.Type: GrantFiled: March 31, 2017Date of Patent: July 20, 2021Assignee: Intel CorporationInventors: Robert Alan May, Kristof Darmawikarta, Sri Ranga Sai Sai Boyapati
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Patent number: 11069821Abstract: A semiconductor device and its manufacturing method are presented. The manufacturing method entails: providing a semiconductor substrate, wherein the semiconductor substrate comprises a first region and a second region that are mutually exclusive from one another, with a first oxide layer on the first and the second regions; conducting a nitriding process on the semiconductor substrate to form a nitride barrier layer on the first oxide layer on the first and the second regions; removing the first oxide layer on the second region; and conducting an oxidation process to form a second oxide layer on the second region.Type: GrantFiled: July 3, 2019Date of Patent: July 20, 2021Inventors: Guo Bin Yu, Xiao Ping Xu