Abstract: An amplifier circuit is disclosed for providing a radio frequency output signal having a variable signal envelope, comprising a main amplifier device and an auxiliary amplifier and a combiner network for combining an output signal from said first amplifier device and a second output signal from said second amplifier device to provide a combined output signal of variable signal envelope to a load, and a signal processing circuit comprising an input and a non-linear processing section to provide at least said second radio frequency output signal with a signal envelope that has a non-linear dependency from an amplitude characteristic of the input signal such that the degree of non-linearity of the non-linear dependency varies dependent on the amount of change per time unit of the amplitude characteristic of the input signal. Further, a method of power amplifying a radio frequency signal having a variable signal envelope is disclosed.

Abstract: A power amplifier circuit (DIPPA), comprising a driver stage (DR) which is applicable to provide a preamplified driver signal (S_DR) dependent on a predetermined transmit signal. The power amplifier circuit (DIPPA) comprises also a frequency selector (DIP) which is electrically coupled to the driver stage (DR) and which is applicable to separate the driver signal (S_DR) into a first and second signal (S—1, S—2). The first signal (S—1) is associated to a first predetermined and the second signal (S—2) is associated to a second predetermined frequency band. The power amplifier circuit (DIPPA) comprises at least a first and second power amplifier stage (PA1, PA2). The first and second power amplifier stage (PA1, PA2) are electrically coupled to the frequency selector (DIP). The first and second power amplifier stage (PA1, PA2) is operable to provide a first and second amplified signal (S_A1, S—2), respectively, dependent on the first and second signal (S—1, S—2), respectively.

Abstract: The differential trans-impedance amplifier uses trans-resistance(s) connected between the input nodes of a first differential amplifier, to implement a trans-impedance differential amplifier in a differential fashion and has two identical resistances, each connected between the photodiode and a respective DC voltage rail of a common bias network of the photodiode adapted to reverse bias the photodiode. The biasing resistances may be much larger than the trans-resistance(s) to prevent drawing any significant signal current from the photodiode. The amplifier may retain the advantages of a classical differential topology while effectively overcoming drawbacks that arise in high data rate applications.

Abstract: The embodiments of the present invention disclose a variable gain amplifier and relate to the field of electronic circuits. The linear-in-dB relationship between an output current and a control voltage of the variable gain amplifier is relatively ideal. The variable gain amplifier includes a fitted differential module group and an offset voltage output module, where the fitted differential module group is configured to output, under the control of a driving voltage and offset voltages, an output current of the variable gain amplifier according to a reference current; and the fitted differential module group includes n fitted differential modules, the n fitted differential modules are cascaded in turn, and n is any positive integer larger than 1.

Abstract: A traveling wave amplifier (TWA) with suppressed jitter is disclosed. The TWA includes a plurality of unit amplifiers with the differential arrangement comprised of a pair of transistors and a cascade transistors connected in series to the switching transistors. The unit amplifiers further includes current sources to provide idle currents to the cascade transistors. Even when the switching transistors fully turn off, the idle currents are provided to the cascade transistors, which set the operating point of the cascade transistor in a region where an increase of the base-emitter resistance is suppressed.

Abstract: Embodiments are directed to capacitance compensation via a compensation device coupled to a gain device to compensate for a capacitance change occurring due to an input signal change, along with a controller coupled to the compensation device to receive the input signal and to control an amount of compensation based on the input signal. In some embodiments, banks may be formed of multiple compensation devices, where each of the banks has a different size and is coupled to receive a different set of bias voltages.

Abstract: Disclosed is a signal splitting apparatus useable in a power amplifier having two or more power amplifiers. The apparatus includes a direct gain component; and a derived gain component connected to the direct gain component. The derived gain component derives the derived gain by imposing a constraint which is valid over the entire dynamic range of the input signal, e.g. the sum of the power of the direct split signal and the derived split signal are constrained to be substantially equal to the power of the input signal. The use of combining additional direct gain and derived gain components, as well as a delay element, are disclosed so as to enable n-component splitting that for adaptation to different applications by the use of suitable coefficients.

Abstract: There is provided a bias arrangement for an amplifier adapted to amplify a varying input signal, the arrangement comprising a control circuit arranged to adaptively vary a bias current to the amplifier in dependence on an envelope of the varying input signal.

Abstract: An apparatus is provided that includes first and second ICs configured to communicate using a plurality of differential signal lines. The apparatus includes a common mode suppression circuit having a plurality of common mode voltage adjustment circuits, each configured to provide a low impedance path for common mode signals and a high impedance path for differential AC signaling, thereby suppressing the effect of common mode transients between the voltage domains. The plurality of common mode voltage adjustment circuits each have components that are impedance matched up to an impedance-tolerance specification. The common mode suppression circuit also includes an AC coupling circuit configured to be less dependent on impedance mismatch, beyond the impedance-tolerance specification, by cross coupling the impedance differentials from each of the differential signal lines through the AC coupling circuit and to one of the common mode voltage adjustment circuits.

Abstract: Techniques for monitoring and controlling bias current of amplifiers are described. In an exemplary design, an apparatus may include an amplifier and a bias circuit. The amplifier may include at least one transistor coupled to an inductor. The bias circuit may generate at least one bias voltage for the at least one transistor in the amplifier to obtain a target bias current for the amplifier. The bias circuit may generate the at least one bias voltage based on a voltage across the inductor in the amplifier, or a current through a current mirror formed with one of the at least one transistor in the amplifier, or a gate-to-source voltage of one of the at least one transistor in the amplifier, or a voltage in a replica circuit replicating the amplifier, or a current applied to the amplifier with a switched mode power supply disabled.

Abstract: A power amplifier includes a first matching circuit configured to perform harmonic processing of an input signal, and a second matching circuit configured to perform the harmonic processing of an output signal, the output signal being generated by amplifying a power of the input signal. The power amplifier rotates a phase of output impedance at a matching point of the harmonic included in the generated output signal when the power of the input signal is decreased from a value higher than a certain value to a value lower than the certain value.

Abstract: A method of reducing stress in a cascode common-source amplifier including a first transistor and a second transistor connected in a cascode arrangement. The method includes providing an input voltage and a bias voltage to the first transistor and the second transistor, respectively, connected in the cascode arrangement, generating, based on the input voltage and the bias voltage, an output current, and equalizing stress associated with operation of each of the first transistor and the second transistor. Equalizing the stress includes, in response to the input voltage decreasing by an amount sufficient to cause the first transistor and the second transistor to turn off, equalizing respective voltage drops across the first transistor and the second transistor.

Abstract: A control circuit and a method for controlling an operation of a power amplifier core are provided. The power amplifier core is switchable between an envelope tracking operation mode and a non-envelope tracking operation mode. The control circuit is configured to provide a control signal for controlling the operation of the power amplifier core or to process an amplified signal received from the power amplifier core in dependence on the operation mode of the power amplifier core.

Abstract: A signal processing circuit has a first circuit, a digital-to-analog converter (DAC) and a second circuit. The first circuit receives a digital input signal with a non-zero direct current (DC) component, and subtracts at least a portion of the DC) component of the received digital input signal from the received digital input signal. The DAC is operably coupled to the first circuit, and arranged to perform a digital-to-analog conversion upon an output of the first circuit. The second circuit is operably coupled to the DAC, and arranged to add a DC component to an analog output signal derived from an output of the DAC. The signal processing circuit may be part of an integrated circuit or a wireless communication unit.

Abstract: An amplifier circuit includes a digital amplifier configured to amplify an input signal to output a first output signal, an analog amplifier configured to amplify the input signal to output a second output signal, a check circuit configured to produce a check signal responsive to frequencies of the input signal, and a selector circuit configured to select and output one of the first output signal and the second output signal in response to the check signal.

Abstract: A method to mitigate interference in a wireless system is provided. The method includes processing a set of radio network identifiers and limiting a number of hypotheses associated with the radio network identifiers in order to mitigate interference in a wireless network. In another aspect, the method includes processing a set of hypotheses and limiting the set of hypotheses by limiting a number of downlink grants to a common space, limiting the number of downlink grants to a number of instances, or limiting the number of grants to a physical downlink control channel (PDCCH) type. In yet another aspect, the method includes processing a downlink set and generating a target termination level for the downlink data set, the termination level associated with a Hybrid automatic repeat-request.

Abstract: A driver for an analog-to-digital converter (ADC) has an overall feedback loop between its input and its output for maintaining overall accuracy, and a much faster feedback loop in its output stage that quickly compensates for output transients before the overall feedback loop can substantially react to the transients. Output voltage transients are created by the intermittent capacitive load of the ADC. The fast feedback loop can be made very fast since there are only a few components in the fast feedback path. The fast reduction of the output transients enables a shorter sampling time, leading to more accurate analog-to-digital conversion. The overall gain of the driver can be set to be greater than unity while still providing good output transient suppression.

Abstract: A voltage converter can be switched among two or more modes to produce an output voltage tracking a reference voltage that can be of an intermediate level between discrete levels corresponding to the modes. One or more voltages generated from a power supply voltage, such as a battery voltage, can be compared with the reference voltage to determine whether to adjust the mode. The reference voltage can be independent of the power supply voltage.

Abstract: Embodiments provide a DC-DC converter (DC-DC=direct current to direct current) for envelope tracking. The DC-DC converter includes a digital control stage and a driving stage. The digital control stage is configured to provide a digital control signal based on digital information describing an amplitude of a digital baseband transmit signal. The driving stage is configured to provide a supply voltage for an RF amplifier (RF=radio frequency) based on the digital control signal.

Abstract: Some embodiments provide an amplifier apparatus, comprising: a plurality of amplifier transistor circuits coupled in series, wherein each of the plurality of amplifier transistor circuits comprises: a transistor, wherein the transistors of the plurality of amplifier transistor circuits are coupled in series; a transistor voltage control and drive circuit coupled with the corresponding transistor, wherein the transistor voltage control and drive circuit is configured to control and drive the corresponding transistor in accordance with received control signals and in parallel with the other of the plurality of amplifier transistor circuits; and isolation circuitry that isolates control of the transistor from control of the other of the amplifier transistor circuits; wherein the plurality of amplifier transistor circuits are configured to be controlled and driven in parallel relative to the control signals.