Abstract: A switched-capacitor DC blocking amplifier is disclosed. In an embodiment, an integrated circuit is provided that includes an amplifier having an amplifier input and an amplifier output, a capacitor connected to the amplifier input and configured to receive an input signal, and a switched capacitor circuit coupled to provide a resistance between the amplifier input and the amplifier output. In one implementation, the switched capacitor circuit is configured with a feed forward circuit to reduce aliasing. In another implementation, the switched capacitor circuit includes a switched impedance circuit to reduce noise.

Abstract: One or more embodiments of a method and apparatus taught herein provide a predistortion system to compensate for the non-linearity of a power amplifier. The system includes an outer predistorter, an inner predistorter, and a first adaptation circuit. The predistorter predistorts an input signal to generate a first output signal, and uses a first memory model that models power amplifier memory effects within a first range of time constants. The inner predistorter predistorts the first output signal to generate a second output signal, and uses a second memory model that models power amplifier memory effects within a second range of time constants that is greater than the first range of time constants. The second output signal is provided as an input to the power amplifier, and the first adaptation circuit adapts the outer predistorter responsive to feedback from the power amplifier.

Abstract: To provide an envelope tracking type amplifier that has high efficiency and small fluctuations, an output unit supplies an output signal that is adjusted corresponding to an input signal to a power supply terminal of the amplifier. The output unit includes an analog amplifying circuit that amplifies the input signal; a digital circuit that selectively outputs a first voltage or a second voltage that is lower than the first voltage; and first and second output circuits. The first output circuit includes a first integrating circuit that integrates an output signal of the digital circuit; and a combining section that combines an output signal of the first integrating circuit and an output signal of the analog amplifying circuit and outputs the combined signal to a power supply terminal of the amplifier.

Abstract: An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.

Abstract: Embodiments disclosed in the detailed description relate to a pseudo-envelope follower power management system including a parallel amplifier and a switch mode power supply converter cooperatively coupled to generate a power supply voltage at a power supply output coupled to a linear RF power amplifier. The parallel amplifier output is in communication with the power amplifier supply output. The parallel amplifier governs operation of the switch mode power supply converter and regulates the power amplifier supply voltage base on a VRAMP signal. The parallel amplifier circuit includes an open loop high frequency compensation assist circuit that generates a high frequency ripple compensation current based on an estimate of the high frequency ripple currents contained in a ripple current of the power inductor. The high frequency ripple compensation current is injected into the parallel amplifier circuit output to cancel out high frequency ripple currents at the power amplifier supply output.

Abstract: An amplifier circuit (10) comprises a driver stage (11) with a driver output (13). Moreover, the amplifier circuit (10) comprises a sensor (12). The sensor (12) comprises a variable attenuator (15) with a control input (16) for receiving a mode signal (SMODE). A sensor output (14) of the sensor (12) is coupled to the driver output (13) via the variable attenuator (15). A sensor signal (SE_RFOUT) is provided at the sensor output (14).

Abstract: Disclosed is a signal splitting apparatus useable in a power amplifier having two or more power amplifiers. The apparatus includes a direct gain component; and a derived gain component connected to the direct gain component. The derived gain component derives the derived gain from the direct gain by imposing a constraint which is valid over the entire dynamic range of the input signal, e.g. the sum of the power of the direct split signal and the derived split signal are constrained to be substantially equal to the power of the input signal. The use of combining additional direct gain and derived gain components, as well as a delay element, are disclosed so as to enable n-component splitting that for adaptation to different applications by the use of suitable coefficients.

Abstract: Communication techniques enable efficient communication to UE (User Equipment) that is subject to a dominant interference signal that is transmitted by a different base station. Disclosed interference cancellation techniques, both UE-centric and network-centric, are suitable to this situation. These techniques are particularly advantageous when it is undesirable or difficult to introduce changes in the physical (PHY) and medium access control (MAC) layers at the existing base stations. An UE-centric framework refers to an approach largely implemented by UEs to include pico or femto cells. Network-centric framework closed-loop coordination between base stations and UEs achieves interference mitigation thereby improving network performance.

Abstract: A digital pre-distortion system and method are provided. The method includes performing a digital pre-distortion operation; and limiting an input of the power amplifier to be no greater than a limit threshold.

Abstract: Methods and apparatus are described for mitigating intercell interference in wireless communication systems utilizing substantially the same operating frequency band across multiple neighboring coverage areas. The operating frequency band may be shared across multiple neighboring or otherwise adjacent cells, such as in a frequency reuse one configuration. The wireless communication system can synchronize one or more resource allocation regions or zones across the multiple base stations, and can coordinate a permutation type within each resource allocation zone. The base stations can coordinate a pilot configuration in each of a plurality of coordinated resource allocation regions. Subscriber stations can be assigned resources in a coordinated resource allocation region based on interference levels. A subscriber station can determine a channel estimate for each of multiple base stations in the coordinated resource allocation region to mitigate interference.

Abstract: A multiport amplifier and a wireless device using the same are obtained in which isolation among output terminals is improved, whereby the quality of communication is improved. The multiport amplifier includes an input hybrid, an output hybrid, a plurality of amplifiers and a plurality of gain and phase control circuits that are inserted between the input hybrid and the output hybrid, a plurality of output coupling circuits that are inserted between the output hybrid and a plurality of output terminals so that they receive output extraction signals corresponding to a plurality of output signals, and a feedback circuit including a frequency selection circuit that is inserted between the plurality of output coupling circuits and the plurality of gain and phase control circuits.

Abstract: This invention discloses circuit and methods of a NAND-based 2T-string NOR flash cell structure as a building block for a fast random-read NOR flash memory. The key concept of this new set of bias conditions in cell array improves over the critical concern of punch-through issue when cell is migrating to the more advanced technology node of next generation. The invention adopts a novel preferable symmetrical 2T-string NOR flash cell. Each NAND or NAND like cell of this 2T-string NOR cell is to store 2 bits and is preferable to be made of N-channel device. The cell is preferable to use Fowler-Nordheim Tunneling scheme for both erase and program operations- The invention is to provide a novel 2T-string NOR flash cell structure made of N-channel device offering most flexible erase sizes in unit of byte, page, sector, block and chip with the least program and erase disturbances.

Abstract: A radio frequency (RF) amplifier structure provides highly efficient RF signal amplification across a wide bandwidth, when implemented in both inverting and non-inverting Doherty designs, by employing matching impedance transform circuits that comprise a low pass multiple section inductance-capacitance circuit and that provides impedance matching between the output of an amplifier device and a power combiner, wherein the output matching impedance transform circuit has approximately an odd multiple of 90 electrical degrees over the RF amplifier structure's frequency range of operation, and adjustable phase delay circuits that route an amplified RF signal to the power combiner and that are controllably adjusted based on a frequency of an RF input signal over an operating frequency range of the RF amplifier structure.

Abstract: Disclosed is a method and apparatus for linearizing a power amplifier using a digital signal process (DSP), and particularly, is a method and apparatus for effectively linearizing an amplifier which has a plurality of distortion generating sources. To this end, there is a plurality of compensation methods and compensation units which can generate inverse distortion signals corresponding to the distortion components outputted by the plurality of distortion generating sources, thereby making it possible to provide superior linearity.

Abstract: An analog pre-distortion linearizer having predetermined gain and phase characteristics as a function of input RF signal power is disclosed. The linearizer comprises a core circuit comprising an input terminal configured to receive an input RF signal; an output terminal configured to provide a processed version of that signal; a transistor having a gate, a drain, and a source; and a feedback circuit, presenting an impedance at the frequency of the RF signal, connected to the transistor. The gate is connected to the input terminal and the drain is connected to the output terminal. First and second dc bias voltages applied to the gate and drain respectively cause the transistor to operate at a quiescent bias point in a saturated region of the transistor I-V plane. The quiescent bias point and the impedance are selected such that the linearizer has the predetermined gain and phase characteristics.

Abstract: Embodiments of the present invention provide a sample and hold amplifier that provides a preamplifier with a multi-stage zeroing architecture. The multi-stage architecture reduces effects of parasitic capacitance exponentially over prior attempts, which yields increased accuracy.

Abstract: Provided is an analog amplifier for amplifying an analog signal and an analog filter, and in particular, an apparatus and method for controlling gain and cutoff frequency of the variable gain amplifier and the variable cutoff frequency filter that is capable of changing the gain and cutoff frequency. The variable resister includes a plurality of resister segments in the variable resister and, when a plurality of resistance candidates for the variable resister are arranged in order of size, the resistance candidates form a geometric series.

Abstract: There is provided an amplification stage comprising: an input scaling block for scaling an input signal in dependence on an input scaling factor to generate a scaled version of the input signal; a power amplifier for generating an amplified version of the scaled input signal; an envelope detector for generating a signal representing the envelope of the input signal; an envelope scaling block for scaling the envelope signal in dependence on an envelope scaling factor to generate a scaled version of the envelope signal; a non-linear mapping block for generating a voltage representative of the supply voltage in dependence on the scaled envelope signal; a modulator for generating a power supply voltage for the amplifier in dependence on the voltage generated by the non-linear mapping block; and a power control block for maintaining a linear relationship between the envelope scaling factor and the input scaling factor.

Abstract: An amplifier assembly includes an input signal determiner that determines a first input signal and a second input signal based on an initial signal having an amplitude and an initial frequency. Amplifiers amplify the first and second input signal to form first and second output signals having a phase offset with respect to one another. The first and second amplified output signals are fed to a common coupling element that forms a useful signal and a loss signal, such that a total power of the useful signal and loss signal is independent of the phase offset, the power of the useful signal has a maximum corresponding to a predetermined value of the phase offset, and the partial power of the useful signal decreases with a deviation of the phase offset from the predetermined value.

Abstract: Power reduction in transmitters is very important. One method to realize reduction is to make use of switching power amplifiers (PA) that have a better efficiency. Switching PA concepts are only possible in combination with suitable modulation methods like pulse width modulation (PWM) and out-phasing concepts. However, PWM and out-phasing concepts rely on accurate phase control and duty cycle of the signals. Digitally generation of signals of variable duty cycles and phase is proposed without sacrificing their accuracy. Accordingly, a out-phasing power amplifier arrangement is disclosed, where the generation of the out-phasing angle (?) and duty cycles (d1 and d2) are controlled by a set of n-bit digital input words (D1, D2, D3, D4). The baseband phase information (?(t)) is phase modulated back to radio frequency and used as the clock signal of digital circuitry for phase and duty cycle generation after being frequency multiplied by 2n-1.