Patents Examined by Patrick Chen
  • Patent number: 10205459
    Abstract: Described is an apparatus comprising: a multi-modulus divider; and a phase provider to receive a multiphase periodic signal and operable to rotate phases of the multiphase periodic signal to generate an output which is received by the multi-modulus divider.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 12, 2019
    Assignee: Intel Corporation
    Inventor: Mingwei Huang
  • Patent number: 10199831
    Abstract: In a circuit arrangement for in-line supply of voltage to an electrical or electronic apparatus located in the region of a DC line, a parallel circuit of two diodes oriented in anti-parallel is arranged in the line. When a direct current is flowing between terminals of the circuit arrangement, the anti-parallel diodes permit a small voltage drop between the terminals, irrespective of the direction of flow of the current, which voltage drop is limited to the forward voltage of the diode that is currently forward biased. The voltage drop across the anti-parallel diodes is tapped by a supply subcircuit. A semiconductor switch can be connected in parallel with the anti-parallel diodes, which switch is controlled by a voltage-reduction subcircuit to minimize the power dissipation of the circuit arrangement.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: February 5, 2019
    Assignee: SMA Solar Technology AG
    Inventor: Markus Hopf
  • Patent number: 10193560
    Abstract: A charge pump includes: (I) a current source; (II) a p-channel source current network including: a first p-channel transistor; a second p-channel transistor; a p-channel current switch including at least one source terminal coupled to the drain terminal of the first p-channel transistor, at least one gate coupled to a phase comparator, and at least one drain terminal; a third p-channel transistor; and (III) a n-channel sink current network including: a first n-channel transistor; a second n-channel transistor; a third n-channel transistor; a n-channel current switch comprising at least one drain terminal coupled to the source terminal of the third n-channel transistor, at least one gate coupled to the phase comparator; and at least one source terminal coupled to the drain terminal of the first n-channel transistor; and wherein the p-channel source current network and the n-channel sink current network draw a baseline current from the first p-channel transistor.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 29, 2019
    Assignee: Analog Bits Inc.
    Inventors: Alan C. Rogers, Raghunand Bhagwan
  • Patent number: 10170460
    Abstract: Embodiments of the present invention provide systems and methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alain F. Loiseau, Steven W. Mittl, Andreas D. Stricker
  • Patent number: 10153774
    Abstract: A phase locked loop (PLL) circuit and a method for providing a transconductance in the PLL involve forming an input voltage to an operational amplifier by a loop filter. A voltage output of the operational amplifier controls a plurality of current mirrors. A current is formed through a first one of the current mirrors as a function of the input voltage, a resistance of a resistor, and a reference voltage. The reference voltage is directly provided by, or derived from, a reference signal. A second voltage formed in the first current mirror is fed back to the operational amplifier to maintain the current through the first current mirror, which current is then mirrored into at least a second one of the current mirrors to form an output current proportional to a difference between the input voltage and the reference voltage.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: December 11, 2018
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Scott David Huss, Mark Alan Summers
  • Patent number: 10148260
    Abstract: Methods, devices, techniques, and circuits are disclosed for fast current control of a buck converter. In one example, a device includes a pulse density modulator, an analog comparator, and an interconnect circuit. The analog comparator has a first input connected to a peak current reference. The interconnect circuit has a first input connected to an output of the pulse density modulator and a second input connected to an output of the analog comparator. The device has an output terminal of the interconnect circuit.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: December 4, 2018
    Assignee: Infineon Technologies AG
    Inventors: Attila Tomasovics, Arno Rabenstein
  • Patent number: 10133284
    Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: November 20, 2018
    Assignee: SK hynix Inc.
    Inventors: Seung Hun Lee, Won Kyung Chung
  • Patent number: 10097163
    Abstract: A low order filter circuit having a frequency correction function, a frequency correction method for a low order filter circuit, and a high order filter circuit are provided. An analog to digital converter (ADC) may detect a peak of a signal processed by a second order filter unit, and after comparison and determination are performed by a digital correction unit, a frequency control signal is outputted as a feedback to a notch filter or a band-pass filter in the second order filter unit where frequency adjustment is performed. The high order filter circuit is integrated by a plurality of the low order filter circuits. Before correcting the high order filter circuit, switch units may restore the high order filter circuit to the low order filter circuits for correction, and then combine the corrected low order filter circuits to form the original high order filter circuit.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: October 9, 2018
    Assignees: NUVOTON TECHNOLOGY CORP., NCKU RESEARCH & DEVELOPMENT FOUNDATION
    Inventors: Shuenn-Yuh Lee, Sz-An Chen
  • Patent number: 10090827
    Abstract: A flip-flop includes a pulse-generator and a pulse-controlled latch. The pulse generator includes a first inverter to invert a clock signal, a second inverter to invert the inverted clock signal to generate a delayed clock signal, and a NOR gate having a first input coupled to an output of the first inverter, a second input coupled to the output of the second inverter, and an output, which, in operation, provides a pulse signal in response to a rising edge of a received clock signal. The pulse-controlled latch circuit has a data input and is controlled by the pulse signal and the delayed clock signal. The flip-flop may include a multiplexer to select an input signal.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: October 2, 2018
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Patrik Temleitner, Fady Abouzeid
  • Patent number: 10079502
    Abstract: A power management system for dispensers is described. The system includes a controller connected to a lower power zero net voltage (ZNV) power source. A power rectification circuit (PRC) converts ZNV power to higher voltage direct current (HVDC) power. An energy storage system connected to the HVDC power source receives and stores HVDC power within the energy storage system which is selectively provided to a dispenser motor load connected to the energy storage system. The system provides an effective solution to the problem of transferring power from a low power battery source on a disposable product to a dispenser as well as providing a system that minimizes corrosion at the electrical interface between the disposable product and the dispenser particularly in higher humidity environments.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: September 18, 2018
    Assignee: Smart Wave Technologies, Inc.
    Inventors: Peter Zosimadis, Paul Waterhouse
  • Patent number: 10033393
    Abstract: A stacked synthesizer for wide local oscillator (LO) generation using a dynamic divider. The phase locked loop can include a plurality of voltage controlled oscillators (VCOs), and a selector that can be configured to select an output of one of the plurality of VCOs. The selected output of one of the plurality of VCOs can be provided to an on-chip dynamic divider and to an off-chip dynamic divider for LO sharing. The dynamic dividers can be configured to generate synthesizer outputs based on a multiplication of the selected output of one of the plurality of VCOs by a factor (1+1/M), where M is a variable number.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: July 24, 2018
    Assignee: MAXLINEAR ASIA SINGAPORE PTE LTD
    Inventors: Igal Kushnir, Hung-Ming Chien, Wei-Hong Chen, Theodoros Chalvatzis, Seunghwan Yoon, Chin-Ming Chien, Tirdad Sowlati, Moche Cohen, Kobi Sturkovich, Shaul Klein
  • Patent number: 10033377
    Abstract: Systems, circuits, and methods for operating an Insulated-Gate Bipolar Transistor (IGBT) are provided. A circuit is to include a first driver for the IGBT, the first driver having a first resistance and being connectable to the gate of the IGBT. The circuit is further described to include a second driver for the IGBT, the second driver having a second resistance different from the first resistance and also being connectable to the gate of the IGBT. The circuit is also described to include a controller that receives at least two inputs regarding operating characteristics of the IGBT and based on the at least two inputs decides whether to connect the first or second driver to the gate of the IGBT during power-down of the IGBT.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: July 24, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Yunfeng Liang, Bin Zhang
  • Patent number: 10033370
    Abstract: A drive circuit for driving a semiconductor switch includes an overload detector circuit connected to the semiconductor switch and designed to detect an overload state of the semiconductor switch. The drive circuit further includes a driver circuit connected to a control terminal of the semiconductor switch and designed to generate, upon detection of an overload state, a driver signal having a level such that the semiconductor switch is switched off or switch-on is prevented. The driver circuit is further designed to generate a driver signal for driving the semiconductor switch according to a control signal, wherein for switching on the transistor at a first instant a driver signal is generated at a first level and, if no overload state is detected up to a predefined time period having elapsed, the level of the driver signal is increased to a second level.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: July 24, 2018
    Assignee: Infineon Technologies AG
    Inventors: Christian Jaeger, Johannes Georg Laven
  • Patent number: 10020802
    Abstract: An integrated circuit is provided with an MCU, which is configured to generate a PWM control signal that is free of switching pattern information therein. A current-estimating gate driver is provided, which is responsive to the PWM signal. This gate driver is configured to drive first and second gate terminals of first and second parallel switching devices (within a hybrid switch) with gate signals that establish a second switching pattern within the hybrid switch. These gate driving operations are performed in response to measuring a first voltage associated with a terminal of the hybrid switch when being driven by gate signals that establish a first switching pattern within the hybrid switch that is different from the second switching pattern. The duty cycles of the gate signals associated with the second switching pattern are unequal and the duty cycles of the gate signals associated with the first switching pattern are unequal.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: July 10, 2018
    Assignee: Eaton Intelligent Power Limited
    Inventors: Tiefu Zhao, Jiangbiao He, Yakov Lvovich Familiant, Mengbin Ben Yang
  • Patent number: 10014866
    Abstract: A master-slave delay locked loop system comprises a master delay locked loop (“MDLL”) for generating at least one bias voltage and at least one slave delay locked loop (“SDLL”). The at least one SDLL is coupled to the MDLL, where the at least one SDLL comprises an analog to digital converter for converting the at least one bias voltage to at least one digital signal, an adder/subtractor block for adjusting the at least one digital signal based on at least one control signal, a digital to analog converter for converting the at least one adjusted digital signal to at least one analog signal, a voltage to current converter for converting the at least one analog signal to at least one bias current, delay elements for generating phase delayed signals based on the at least one bias current, and a phase detector and control logic for determining any phase difference between the phase delayed signals and for generating the at least one control signal to align the phase delayed signals.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: July 3, 2018
    Assignee: Invecas, Inc.
    Inventors: Narasimhan Vasudevan, Venkata N. S. N. Rao, Prasad Chalasani
  • Patent number: 9998107
    Abstract: This application relates to an active diode circuit for letting current pass in one direction and blocking current in the opposite direction. The active diode circuit comprises a transistor, a control voltage generation circuit for generating a control voltage that is supplied to a control terminal of the transistor, and a sensing circuit for detecting a quantity indicative of a current flowing through the transistor. The control voltage generation circuit generates the control voltage in dependence on the detected quantity. The application further relates to a method of controlling a transistor to function as an active diode so that current may pass in one direction and is blocked in the opposite direction.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 12, 2018
    Assignee: Dialog Semiconductor (UK) Limited
    Inventor: Shafqat Ali
  • Patent number: 9994109
    Abstract: A boost converter is configured of a boost chopper having a diode of an upper arm and a switching element of a lower arm. Output power from a battery to a load is limited such that a current flowing through boost converter does not exceed a current upper limit value for thermal protection of boost converter. The current upper limit value is set based not only on a cooling water temperature of boost converter but also on an output voltage VH of boost converter, in consideration of characteristics that, as output voltage VH rises, an amount of heat generated in diode decreases, diode being regarded as a main target of thermal protection since it receives a power running current to load. Thereby, the boost converter can be protected from overheating without excessively deteriorating vehicle traveling performance.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 12, 2018
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Etsushi Taguchi, Akihiro Takahashi
  • Patent number: 9989984
    Abstract: A reference voltage circuit is provided, which includes bandgap reference circuit, bias current generator, first capacitor, second capacitor, comparator and control logic circuit. In the active mode of the control logic circuit, the control logic circuit controls the bandgap reference circuit to deliver bandgap reference voltage. The comparator transmits first comparison signal to control logic circuit when the first and second capacitors are charged to the bandgap reference voltage. The control logic circuit enters low power mode and controls the bandgap reference circuit to stop delivering the bandgap reference voltage. If the comparator detects the potential difference between the first capacitor and second capacitor exceeds the threshold value, the control logic circuit returns to active mode according to the second comparison signal transmitted form the comparator.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: June 5, 2018
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Te-Ming Tseng, Wei-Chan Hsu, Yeh-Tai Hung, Wen-Yi Li
  • Patent number: 9985619
    Abstract: A duty cycle corrector (DCC) includes a duty corrector circuit configured to adjust a duty of an input signal to output a duty-adjusted signal; a duty detector circuit configured to generate a correction code associated with the adjustment of the duty, based on a charge pump operation and a counting operation; and a timing controller configured to generate a first control signal associated with the charge pump operation and a second control signal associated with the counting operation in synchronization with a first clock.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hoon Lee, Joung-wook Moon, Seong-hwan Jeon
  • Patent number: 9978743
    Abstract: Embodiments of the present invention provide methods for balancing voltages during voltage division. More specifically, circuit performance is enhanced (i) balancing out the voltage drops across two field effect transistors (FETs); (ii) powering inverters through a voltage divider containing two voltage input pins during normal operation of the circuit; and (iii) powering inverters through a FET during electrostatic discharge.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: May 22, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alain F. Loiseau, Steven W. Mittl, Andreas D. Stricker