Abstract: In accordance with an embodiment, method of controlling a switching transistor includes applying a first voltage to a first node of a switchable tank circuit, where the first node is coupled to a control node of the switching transistor, the first voltage has a first polarity with respect to a reference terminal of the switching transistor, and the first voltage is configured to place the switching transistor into a first state. After applying the first voltage, the switchable tank circuit is activated, where a voltage of the first node transitions from the first voltage to a second voltage that is configured to place the switching transistor in a second state different from the first state. The switchable tank circuit is deactivated after the voltage of the first node attains the second polarity.

Abstract: An apparatus includes a switch module, a sense circuit coupled to the switch module and configured to indicate an operating conduction mode of the switch module, and a drive circuit operatively coupled to the switch module to enable and disable forward conducting mode of the switch module. Once the switch module is in forward conducting mode, the drive circuit is configured to maintain enablement of the forward conducting mode even if the sense circuit indicates reverse conduction mode.

Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Abstract: A level-shift circuit, receiving a supply voltage and a input signal, includes a pre-stage voltage conversion circuit and a post-stage voltage conversion circuit. The pre-stage voltage conversion circuit includes a first voltage protection module generating an inner conversion voltage and a first voltage conversion module converting the input signal into a pre-stage output signal according to the inner conversion voltage. The post-stage voltage conversion circuit includes a second voltage protection module generating a first inverse output signal, a first output signal, a second inverse output signal, and a second output signal. The transistors of the pre-stage voltage conversion circuit and the post-stage voltage conversion circuit have a punch-through voltage. The level-shift makes the stress of the transistors less than the punch-through voltage when the supply voltage is greater than the punch-through voltage, and remains the driving capability when being less than the punch-through voltage.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a power supply voltage and first data. The second semiconductor device generates a control voltage whose level is adjusted in response to the power supply voltage. The second semiconductor device also receives the first data to generate second data having a swing width different from a swing width of the first data. The second data being driven is controlled by the control voltage.

Abstract: A level shifting circuit can be used to adjust the level of the input signal to a desired output level while maintaining the duty cycle of the input signal. The level shifting circuit can include a capacitor to AC couple the input signal to an inverter that is self-biased at the threshold voltage for the inverter. The AC coupling of the input signal permits the input signal to “ride on” the threshold voltage and transition the inverter between states depending on the value of the input signal. The inverter can be biased at the threshold voltage by connecting the output of the inverter in feedback with the input of the inverter using one or more resistors.

Abstract: An example embodiment includes a fiber optic integrated circuit (IC). The fiber optic IC includes an integrated power supply. The integrated power supply includes a filter, an active switch, and a pulse width modulator (“PWM”). The filter is configured to convert a signal to an output signal of the integrated power supply. The active switch is configured to control introduction of the signal to the filter. The PWM is configured to generate a PWM output signal that triggers the active switch.

Abstract: An integrated circuit with a phase-locked loop (PLL) is provided. The PLL may include a phase frequency detector, a charge pump, a source follower circuit, a variable oscillator, a frequency divider, and a control block. The phase frequency detector may be configured to align or lock a feedback clock signal to a reference clock signal. The control block includes clock loss detection circuits that are used to determine whether the reference clock signal or the feedback clock signal has stopped toggling. In response to detecting a clock loss event for either the reference or the feedback clock signal, the control block may disable the phase frequency detector to place the charge pump in a tristate mode and may apply a predetermined bias voltage to the source follower circuit to help minimize electrical overstress.

Abstract: A semiconductor device may include a first redistribution layer configured to allow for input and output of a first signal through the first redistribution layer. The semiconductor device may include a second redistribution layer configured to allow for input and output of a second signal through the second redistribution layer. The semiconductor device may include a first input/output (I/O) unit configured to input and output the first signal or the second signal through the first I/O unit. The semiconductor device may include a first selection unit configured to selectively couple a connection among the first redistribution layer, the second redistribution layer, and the first I/O unit in response to a logic level of a first selection signal. The semiconductor device may include a first selection signal generation unit configured to generate the first selection signal.

Abstract: A method and apparatus are provided for balancing currents of two or more parallel-connected power semiconductor switches during an on-state of the switches. A control terminal of each switch is driven by a driver unit. The method includes determining ratios between the currents through the switches. For each switch, the method includes controlling the voltage at the control terminal on the basis of the ratios by controlling a level of a supply voltage of the driver unit of the switch, and after a turn-on commutation transient, modulating the output of the driver unit. The duty cycle of the modulation is controlled to minimize the time required for the transition of the voltage at the control terminal from the one voltage level to another.

Abstract: The present disclosure describes apparatuses and techniques of fast transient response for switching power regulators. In some aspects, an output voltage of a switching regulator operating in a discontinuous mode is monitored via a comparator coupled directly to an output of the switching regulator. In response to the output voltage falling below a predefined threshold, a high-side switch is activated to provide current to a load connected to the output of the switching regulator. The switching regulator is then transitioned from the discontinuous mode of operation to a continuous mode of operation to control subsequent operation of the high-side switch. This can be effective to mitigate a drop in the output voltage of the switching regulator when an amount of current consumed by the load increases (e.g., a load step).

Abstract: Bootstrap diode circuits are disclosed. Example bootstrap diode circuits disclosed herein include a first diode having a first diode input coupled to a voltage supply and a first diode output. Disclosed bootstrap diode circuits additionally include a second diode having a second diode input coupled to the first diode output and a second diode output and a plurality of zener diodes coupled in series. The plurality of series-coupled zener diodes are further coupled in parallel with the second diode.

Abstract: A phase compensation circuit includes: a first circuit that increases phase characteristic of a specific frequency of an electrical signal; a second circuit that decreases the phase characteristic of the specific frequency of the electrical signal; and a limiting amplifier that amplifies an electrical signal that is processed by at least one of the first circuit and the second circuit.

Abstract: Aspects of the disclosure provide a regulator circuit including an output circuit, an error detection circuit and an intermediate circuit. The output circuit is configured to receive a first supply voltage, output and regulate a second supply voltage based on a control signal. The error detection circuit is responsive to the first supply voltage, and is configured to compare the second supply voltage with a reference voltage, and generate an error signal with a voltage level that is indicative of a difference between the second supply voltage and the reference voltage. The intermediate circuit is configured to generate a first electrical current based on the error signal and a second electrical current based on the second supply voltage, combine the first electrical current and the second electrical current to generate a third electrical current, and generate the control signal at least partially based on the third electrical current.

Abstract: Aspects of the disclosure provide a circuit for providing a power supply. The circuit includes a control signal generator circuit and a switch network circuit. The control signal generator circuit is configured to generate a control signal with a voltage level that is a function of an output voltage on a load capacitor. The switch network circuit is coupled with the load capacitor and a flying capacitor to form a charge pump circuit. The switch network circuit is configured to charge the flying capacitor in a charge stage and pump the flying capacitor in a pump stage to generate the output voltage on the load capacitor. The switch network circuit is configured to provide a pump control voltage to the flying capacitor during the pump stage. The pump control voltage has a voltage level that is adjusted based on the control signal to maintain the output voltage to be stable.

Abstract: A voltage dropping apparatus may include: a voltage dropping unit receiving an input voltage, outputting the input voltage in a first mode, and dropping a level of the input voltage in a second mode; a voltage output unit connected to the voltage dropping unit, receiving and outputting the input voltage in the first mode, and receiving and outputting the dropped voltage in the second mode; and a control unit receiving a mode signal and controlling a mode change of the voltage dropping unit and the voltage output unit based on a value of the mode signal.

Abstract: A solar power conversion system includes a photovoltaic array having photovoltaic modules for generating direct current (DC) power. A power converter is provided in the system for converting the DC power to alternating current (AC) power. A transformer is coupled between the power converter and a power grid for transmitting the AC power to the power grid. The transformer is connected to the power grid at the point of common coupling (PCC) and to the power converter at output terminals. A reactance estimation module is provided in the system for estimating a short circuit reactance at PCC based on a small change in a measured voltage at output terminals with respect to a small change in a measured reactive power at the output terminals. Further, a maximum reactive power estimation module estimates a maximum reactive power based on the estimated reactance, the measured voltage at output terminals, and the measured reactive power at the output terminals.

Abstract: An output driver circuit includes a control circuit and first and second transistor legs that are coupled to an output pad. Each of the first and second transistor legs includes a pull-up transistor and a pull-down transistor. The control circuit is coupled to the first and second transistor legs. The control circuit enables the first transistor leg to generate an output signal at the output pad and disables the second transistor leg during a first phase of a cycle. The control circuit enables the second transistor leg to generate the output signal at the output pad and disables the first transistor leg during a second phase of the cycle. The control circuit repeats the first and the second phases of the cycle.

Abstract: Methods and systems for operating a double-base bidirectional power bipolar transistor. Two timing phases are used to transition into turn-off: one where each base is shorted to its nearest emitter/collector region, and a second one where negative drive is applied to the emitter-side base to reduce the minority carrier population in the bulk substrate. A diode prevents reverse turn-on while negative base drive is being applied.

Abstract: A circuit for setting a reference voltage is provided. The circuit includes a reference voltage information storage unit and a reference voltage input/output (I/O) control unit. The reference voltage information storage unit is configured to set a level of a reference voltage according to information stored in a first register or a second register if a training operation starts in a first set mode. The reference voltage I/O control unit is configured to set a level of the reference voltage according to first data or second data if the training operation starts in a second set mode.