Abstract: A parameterized superconducting circuit may include a set of sub-blocks which include superconducting circuitry. Different sub-blocks in the set of sub-blocks may be clocked using clock signals having different phases. Along a first direction, relative locations of the set of sub-blocks may be fixed. Along a second direction, relative locations of the set of sub-blocks may be determined based on a set of parameter values.

Abstract: A storage battery system includes a first storage battery unit. First storage battery unit includes a first converter that converts alternating current and direct current, a first storage battery, and a first controller that controls first converter, and first storage battery unit is interconnected to a system for supplying power. The first controller detects a frequency of the system, and controls first converter such that first storage battery outputs constant active power to the system on the basis of the frequency of the system falling below a first threshold value.

Abstract: A quantum device includes a cryogenic chamber and a quantum computing module positioned within the cryogenic chamber. The quantum computing module includes a silicon substrate and a quantum circuit (QC) die including a qubit integrated circuit. The QC die is attached to the silicon substrate. An electronic circuit (EC) die including an electronic integrated circuit is attached to the QC die such that the qubit integrated circuit and the electronic integrated circuit face each other. The QC die can be fusion bonded to the EC die. A circuit board (CB) includes a power converter configured to convert input power received from a cryogenic chamber feedthrough to output power that is coupled to the QC die and to the EC die.

Abstract: The present disclosure provides a circuit and method for expanding the lock range of injection-locked oscillators. The circuit includes N injection-locked oscillators and a lock detector, where the lock detector includes an alignment monitor, a clock selector, and N self-samplers. A pulse reference signal is inputted into the N injection-locked oscillators, and the output of each injection-locked oscillator is connected to the clock selector and the corresponding self-sampler. The self-samplers sample the outputs of the N injection-locked oscillators and output the sampling results to the alignment monitor. The alignment monitor monitors the sampling results, determines the locking conditions of the injection-locked oscillators, and turns off the unlocked oscillators. The clock selector selects a locked oscillator and transmits the output of the locked oscillator as a system lock.

Abstract: Disclosed herein are embodiments including electrical structures that includes a first cell, a first inductor, a first resistor, and a first shunted Josephson junction. The first inductor is connected in series with the first shunted Josephson junction at a first terminal end of the first inductor and a second terminal end of the first inductor is connected to a feed point of the first cell being powered. A first end of the first resistor having connected to ground and a second end being connected to the first shunted Josephson junction at a terminal of the first shunted Josephson junction that is not connected to the first inductor. A source of an electrical current source that is external to the first cell is connected to the first shunted junction and the first resistor at a common point.

Abstract: An aspect of the disclosure relates to an apparatus including a first field effect transistor (FET) including a first gate configured to receive a first input signal that varies in accordance with a first voltage domain; and a first inverter including a first input configured to receive a second input signal that varies in accordance with a second voltage domain, and a first output configured to generate a first output signal that varies in accordance with the second voltage domain, wherein the first output signal is based on the first and second input signals, and wherein the first FET and the first inverter are coupled in series between first and second voltage rails. Per another aspect, the apparatus includes additional circuitry to allow the apparatus to process signals in accordance with a third voltage domain.

Abstract: A multi-bit flip-flop includes a first bit flip-flop and a second bit flip-flop. The first bit flip-flop includes an input multiplexer that receives a first and second data bits, and outputs one of the first and second data bits as a third data bit; a first transmission circuit; a first latch; a second transmission circuit; and a second latch that outputs a first output data bit. The second bit flip-flop includes an input multiplexer that receives a fourth data bit and the first output data bit, and outputs one of the fourth data bit and the first output data bit as a fifth data bit; a first transmission circuit, a first latch, a second transmission circuit, and a second latch that outputs a second output data bit. The first output data bit is provided from the first bit flip-flop to the second bit flip-flop along an external wire.

Abstract: A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.

Abstract: Systems and methods are disclosed herein for Wireless Power Transfer (WPT) using radiative coupling and dynamic beamforming. In some embodiments, a method of operation of an Energy Transmitter (ET) comprises, for each time period (TPi) of a plurality of time periods ({TPi}i=0,1, . . . , I-1), for each time slot (TSi,j) of one or more time slots ({TSi,j}j=0,1, . . . , J-1), transmitting, during TSi,j of TPi on a frequency fmod(i,2), a radio frequency signal (ST(i,j)) that is modulated with a signature of a particular Energy Harvester (EH). The method further comprises, for each TPi, attempting, during TPi, to receive, from the particular EH on a frequency fmod(i+1,2), a radio frequency signal (SR(i)) that is modulated with the signature of the particular EH. In this manner, continuous WPT is provided. Corresponding embodiments of an ET are also disclosed. Embodiments of a method performed by an EH and corresponding embodiments of an EH are also disclosed.

Abstract: Digital values obtained from an output of a preceding circuit element are temporarily stored and made available for a subsequent circuit element at a controlled moment of time. A digital value is received for temporary storage, as well as a triggering signal, a triggering edge of which defines an allowable time limit before which a digital value must appear at said data input to become available for said subsequent circuit element. A sequence of first and second pulse-enabled subregister stages is used to temporarily store said digital value. Said triggering signal is provided to said first pulse-enabled subregister stage delayed with respect to the triggering signal received by said second pulse-enabled subregister stage. The length of the delay is a fraction of a cycle of the triggering signal.

Abstract: A level shifter can achieve a level shift by a wide margin. The level shifter includes a latch circuit, a clamping circuit, a protection circuit, and an input circuit. The latch circuit is coupled between a high-voltage terminal and a pair of output terminals for outputting a pair of output signals. The clamping circuit is coupled between a medium-voltage terminal and the pair of output terminals and limits the minimum voltage of the pair of output signals to the medium voltage. The protection circuit is set between the latch circuit and the input circuit, and prevents an excessive voltage drop between the input circuit and the pair of output terminals. The input circuit includes an input transistor pair coupled between the protection circuit and a low-voltage terminal having a low voltage. The input transistor pair receives a pair of input signals and operates accordingly.

Abstract: A level shifter circuit is disclosed. The level shifter includes an input circuit configured to receive an input signal generated using a first power supply voltage level and generate, using the first power supply voltage level, a first control signal and a second control signal using the input signal. The level shifter further includes a shifter circuit configured to generate a first shifted signal and a second shifted signal using the first control signal, the second control signal, and second power supply voltage level different than the first power supply voltage level, and a selection circuit configured to select, using a value of a previous output signal and the second power supply voltage level, one of the first shifted signal or the second shifted signal to generate a current output signal.

Abstract: The disclosed method of operation for a data latch (DLATCH) circuit may include receiving, by an input component of the DLATCH circuit, an input signal. The method may additionally include storing, by a combinatorial gate of the DLATCH circuit, a state of the input signal, wherein the combinatorial gate corresponds to at least one of an AND-OR-inverted (AOI22) cell or an OR-AND-inverted (OAI22) cell. The method may further include providing an output signal, by an output component of the DLATCH circuit, wherein the output signal has the state stored by the combinatorial gate. Various other methods, systems, and circuits are also disclosed.

Abstract: Improved voltage level shifters are disclosed capable of achieving substantially higher data transfer speeds with reduced static current than existing cross-coupled voltage level shifters. The voltage level shifters disclosed herein include first stage that translates input voltage signals received from a core circuitry in a first voltage domain to intermediate output voltage signals an intermediate voltage domain, and second stage circuitry that translates the intermediate output voltage signals received from the first stage circuitry in the intermediate voltage domain to output voltage signals in a second voltage domain. The disclosed voltage level shifters are scalable to support various logic voltage levels in the second voltage domain.

Abstract: Example flip-flops comprise a circuit that receives a primary clock signal, generates a clock buffer signal having a series of pulses, each delayed by a set amount of time relative to a corresponding pulse of the primary clock signal, generates an intermediate clock signal based on the primary clock signal and the clock buffer signal, generates inflated low pulse width clock signals, each having a low pulse width that is greater than a low pulse width of the primary clock signal. Latch stages within example flip-flops include one or more components that are controlled by the inflated low pulse width clock signals. Example flip-flops include high-speed flip-flops and standard flip-flops. Larger circuits, such as a clock divider circuits, may incorporate multiple example high-speed flip-flops to improve performance.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: Provided is a level shifter circuit that changes a voltage of a high-frequency input signal to output. Provided is a level shifter circuit provided with a first input terminal and a second input terminal to each of which an input signal having a level between a first potential level and a first reference potential level is input, a first output terminal and a second output terminal from each of which an output signal having a level between a second potential level higher than the first potential level and a second reference potential level is output, a second potential supply node that supplies a voltage at the second potential level, a reference potential supply node that supplies a voltage at the second reference potential level, first and second impedance elements, first to fourth transistors, and first and second nodes, in which each of the first impedance element and the second impedance element includes at least three terminals.

Abstract: A power transmitting apparatus sets, on the basis of transmission power set with the power receiving apparatus, a first threshold for determining whether or not a foreign object exist, and a second threshold lower than the first threshold. The first and second threshold are set so that the difference between the first and second threshold values becomes larger as the set transmission power becomes larger. The power transmitting apparatus determines: that a foreign object exists in a case where the power loss is greater than the first threshold; that a foreign object does not exist in a case where the power loss is less than the second threshold; and that there is a possibility of a foreign object existing in a case where the power loss is between the first threshold and the second threshold.

Abstract: A monitor circuit (301) for monitoring changes in an input digital value of a register circuit comprises a data input (302) configured to receive a copy of the input digital value of said register circuit, and one or more triggering signal inputs (303) configured to receive one or more triggering signals. One or more triggering edges thereof define an allowable time limit before which a digital value must appear at a data input of said register circuit to become properly stored in said register circuit. The monitor circuit comprises a data event (DE) output (305), so that said monitor circuit is configured to produce a DE signal at said DE output (305) in response to a digital value at said data input (302) changing within a time window defined by said one or more triggering signals.

Abstract: In some embodiments of the present disclosure, a delay locked loop includes a coarse delay circuit configured to delay a reference clock signal to generate a first clock signal, a fine delay circuit configured to delay the first clock signal to generate a second clock signal, a first delay circuit configured to delay the second clock signal to generate a third clock signal, a second delay circuit configured to delay the first clock signal to generate a fourth clock signal, a third delay circuit configured to delay the fourth clock signal to generate a fifth clock signal, a phase detector configured to detect a phase difference between the reference clock signal and the fifth clock signal, and a controller configured to adjust, a first delay amount of the coarse delay circuit, a second delay amount of the fine delay circuit and a third delay amount of the third delay circuit.