Abstract: A voltage level shifter includes an input stage with series-connected first and second N-type field effect transistors (NFETs) and an output stage with an inverter connected to an intermediate node between the first and second NFETs. Gates of the first and second NFETs are connected to an output node of the inverter and an input node, respectively. An input voltage signal on the input node toggles between a first voltage and ground. An intermediate voltage signal on the intermediate node toggles between a second voltage (lower than the first voltage) and ground. An output voltage signal on the output node toggles between the second voltage and ground. A capacitor in the input stage is connected between the input and intermediate nodes so that, when the input voltage switches to ground, the intermediate voltage signal is pulled to ground to facilitate switching of the output voltage signal to the second voltage.

Abstract: A method of generating an integrated circuit (IC) layout diagram includes defining first through fourth PMOS transistors in an n-well region, arranging a plurality of conductive regions whereby a bias circuit is configured to include the first and second PMOS transistors and a level shifter is configured to include the third and fourth PMOS transistors, and arranging a plurality of conductive elements whereby a first power domain includes electrical connections to each of the first and third PMOS transistors and a second power domain includes electrical connections to each of the second and fourth PMOS transistors.

Abstract: A latch calibration system includes a latch, a clock circuit and a calibration circuit. Latch latches logic data from a data node in an internal node. Latch includes two transistors respectively coupled between data node and internal node. Clock circuit generates first and second clock control signals. Calibration circuit is coupled to clock circuit and latch, and includes two bootstrap circuits coupled to clock circuit respectively. First bootstrap circuit generates a third clock control signal according to first clock control signal, which is output to a gate of first transistor. a high level of third clock control signal is greater than that of first clock control signal. Second bootstrap circuit generates a fourth clock control signal according to the second clock control signal, which is output to a gate of second transistor. A low level of fourth clock control signal is less than that of second clock control signal.

Abstract: A flip-flop circuit includes a first inverter configured to receive a first clock signal and output a second clock signal, a second inverter configured to receive the second clock signal and output a third clock signal, a master latch including a transmission circuit, and a slave latch including a first feedback inverter. The first feedback inverter includes a first transistor configured to receive the first clock signal and a second transistor configured to receive the second clock signal, and the transmission circuit includes a third transistor configured to receive the third clock signal.

Abstract: A phase lock loop includes a clock multiplier configured to receive a reference clock and output a multiplied clock; a phase detector configured to receive the multiplied clock and a divided clock and output a phase error signal; a loop filter configured to receive the phase error signal and output a control signal; a controllable oscillator configured to output an output clock in accordance with the control signal; and a clock divider configured to receive the output clock and output the divided clock, wherein the clock multiplier is either a frequency doubler or a frequency quadrupler, and a frequency response of the loop filter comprises a first notch at the frequency of the reference clock and a second notch at twice the frequency of the reference clock.

Abstract: A variable circuit includes a switch including a plurality of input terminals and a plurality of output terminals and an external wiring line. The multiple input terminals include a first input terminal to which a first input signal is inputted and a second input terminal to which a second input signal is inputted. The multiple output terminals include a first output terminal from which a first output signal is outputted and a second output terminal from which a second output signal is outputted. The switch is capable of forming at least one internal connection path electrically connecting any one of the multiple input terminals and any one of the multiple output terminals. The external wiring line is disposed outside the switch and is configured to electrically connect the second output terminal to the second input terminal.

Abstract: An integrated circuit includes a clocking transistor, a first enabling transistor, a second enabling transistor, a branch-one transistor, and a branch-two transistor. The first enabling transistor is coupled between the clocking transistor and a first node. The second enabling transistor is coupled between the clocking transistor and a second node. The branch-one transistor is coupled between a first power supply and the first node. The gate terminal of the branch-one transistor is connected to the second node. The branch-two transistor is coupled between the first power supply and the second node. The gate terminal of the branch-two transistor is connected to the first node. Each of the clocking transistor, the first enabling transistor, and the second enabling transistor is a first-type transistor of a reduced threshold. Each of the branch-one transistor and the branch-two transistor is a second-type transistor of a default threshold.

Abstract: An input circuit that recognizes (e.g., buffers) logic level signals (e.g., of an input signal) represented by voltage levels that are lower than a supply voltage of an input circuit, and that exhibits static current draw immunity during stable states of an input signal. In one or more examples, series inverters are provided to buffer an input node and an output node of the input circuit. A voltage domain at the input circuit or output node may be higher than a voltage domain at the input node. Power supply to a first inverter of the series inverters may be turned OFF at least partially responsive to an indication that an output signal is a logic high; and power supply to the first inverter of the series inverters may be turned ON at least partially responsive to an indication that the output signal is a logic low.

Abstract: The present disclosure relates to a phase-locked loop (PLL) based on a charge-sharing locking technique, capable of both fractional-N and integer-N operation. The PLL comprises a voltage pre-setting stage; an oscillator: a shared capacitive load; and a switching network configured for selectively connecting the voltage pre-setting stage to the shared capacitive load during a voltage pre-setting stage for applying an expectant voltage to the capacitive load. The switching network is being further configured for selectively connecting the capacitive load to the oscillator during a charge-sharing locking stage for correcting a phase error in response to a difference between the expected voltage of the capacitor and the voltage of the oscillator. Frequency-tracking and waveform-learning stages are also provided for maintaining PVT (process, voltage, temperature) robustness and for suppressing fractional-N spur, respectively.

Abstract: A data retention circuit is provided in the invention. The data retention circuit includes a master latch circuit, a slave latch circuit, and a control circuit. The control circuit is coupled to the master latch circuit and the slave latch circuit and receives a clock signal from a clock circuit and a power management signal from a power management unit (PMU). In a normal operation mode, the control circuit transmits the clock signal to the master latch circuit and the slave latch circuit. In sleep mode, power to the master latch circuit is switched off and the control circuit transmits the power management signal to the slave latch circuit.

Abstract: A system for count separation of objects comprises a controller, cameras adapted to detect each individual object in a stream of falling objects such that the controller can count the objects, a first receiving location adapted to directly receive the stream of falling objects, a second receiving location adapted to receive objects diverted from the stream of falling objects or to receive the stream of falling objects when the stream of falling objects is diverted from the first receiving location; a mechanical diverter having (a) a first position to not divert the stream of falling objects from the first receiving location and (b) a second position in to divert the stream of falling objects to the second receiving location, and an air blast diverter adapted (a) to divert specific objects or the stream of falling objects to the second location.

Abstract: Voltage level conversion circuits include PMOS pull-down devices or NMOS pull-up devices, and inverters with outputs that determine gate voltages of these devices. The inverters are powered by moving supply voltages, for example complementary supply voltages generated from a pair of cross-coupled inverters. The cross-coupled inverters may implement a data storage latch with the moving supply voltages generated from the internal data storage nodes of the latch.

Abstract: Disclosed is a low-pass filtering system having a phase-lock loop comprising a Park transform circuit, a first low-pass filter, a second low-pass filter, an inverse Park transform circuit, a phase-locked loop filter, and a voltage-controlled oscillator. The Park transform circuit, the first low-pass filter, the second low-pass filter, and the inverse Park transform circuit form a phase detector of a phase-locked loop, since the low-pass filter system of the present invention has the phase-locked loop mechanism, the phase and amplitude of a output signal remain the same with those of the original AC input signal.

Abstract: A level shifter circuit is provided. In some examples, the level shifter circuit includes a first set of transistors and a second set of transistors coupled between first and second power supply nodes. The control terminals of the first and second lower transistors are coupled to an input node. The level shifter circuit also includes a third set of transistors and a fourth set of transistors coupled between first and third power supply nodes. A control terminal of a third lower transistor is coupled to a second intermediate node, and a control terminal of a fourth lower transistor is coupled to a first intermediate node. Control terminals of the first upper transistor and the fourth upper transistor are coupled to a third intermediate node. Control terminals of the second upper transistor and the third upper transistor are coupled to a fourth intermediate node.

Abstract: An output signal generation circuit includes a first pulse generation circuit configured to receive first information and generate a first pulse signal including the first information, the first pulse signal having a first pulse width that is a minimum pulse width of the first pulse signal, a second pulse generation circuit configured to receive second information and the first pulse signal, and generate a second pulse signal in which the second information is superimposed on the first pulse signal, the second pulse signal having a second pulse width smaller than the first pulse width, and an output circuit configured to output the second pulse signal.

Abstract: A data transmission device of an embodiment includes a buffer, a first determination circuit, a first flip-flop, a second flip-flop, and a second determination circuit. The buffer holds input data of a predetermined bit width. The first determination circuit determines whether or not the input data is held in the buffer. The first flip-flop receives output of the first determination circuit as input and operates at one of a rising edge and a falling edge of a second clock signal which is asynchronous with the first clock signal. The second flip-flop receives output of the first flip-flop as input and operates at another of the rising edge and the falling edge of the second clock signal. The second determination circuit determines an error based on a request signal which is synchronized with the second clock signal and output of the second flip-flop.

Abstract: Apparatuses and methods for adjusting a phase mixer circuit are disclosed. An example apparatus includes a shift register that includes a plurality of registers coupled in series to one another. The plurality of registers are grouped into a first group of registers and a second group of registers. The first group of registers includes first and second registers. The second group of registers includes a third register. The first and second registers of the first group of registers are configured to receive in common an output of the third register of the second group of registers so that both the first and second registers store the output of the third register responsive to a shift clock.

Abstract: A novel and useful controlled quantum shift register for transporting particles from one quantum dot to another in a quantum structure. The shift register incorporates a succession of qdots with tunneling paths and control gates. Applying appropriate control signals to the control gates, a particle or a split quantum state is made to travel along the shift register. The shift register also includes ancillary double interaction where two pairs of quantum dots provide an ancillary function where the quantum state of one pair is replicated in the second pair. The shift register also provides bifurcation where an access path is split into two or more paths. Depending on the control pulse signals applied, quantum dots are extended into multiple paths. Control of the shift register is provided by electric control pulses. An optional auxiliary magnetic field provides additional control of the shift register.

Abstract: The present disclosure provides a gate driving circuit, a method for detecting the gate driving circuit, an array substrate and a display apparatus. The gate driving circuit comprises a plurality of cascaded gate driving units, access units, a first signal line and a second signal line. Each access unit is connected to its corresponding gate driving unit and the gate driving unit at the next stage to its corresponding gate driving unit. The access unit corresponding to the gate driving unit at each odd stage is connected to the first signal line such that the first signal line detects an output signal from that gate driving unit via the access unit, and the access unit corresponding to the gate driving unit at each even stage is connected to the second signal line such that the second signal line detects an output signal from that gate driving unit via the access unit.

Abstract: A shift register and a driving method thereof, a gate driving circuit and a display device are provided. The shift register includes: a pre-charge module, connected to a pull-up node and configured to charge the pull-up node in a pre-charge phase; a pull-up control module, connected to the pull-up node and an output terminal and configured to pull up a potential of the pull-up node in an output phase and output a driving signal through an output terminal; a denoising module, connected to the pull-up control module and the output terminal and configured to denoise the output terminal in a touch control phase; a reset module, connected to the pre-charge module, the pull-up node, the denoising module and the output terminal and configured to reset the pull-up node and the output terminal in a reset phase and denoise the pull-up node and the output terminal in a denoising phase.