Abstract: The invention relates to a high voltage resistant edge structure in the edge region of a semiconductor component which has floating guard rings of the first conductivity type and inter-ring zones of the second conductivity type which are arranged between the floating guard rings, wherein the conductivities and/or the inter-ring zones are set such that their charge carriers are totally depleted when blocking voltage is applied. The inventive edge structure achieves a modulation of the electrical field both at the surface and in the volume of the semiconductor body. If the inventive edge structure is suitably dimensioned, the field intensity maximum can easily be situated in the depth; that is, in the region of the vertical p-n junction. Thus, a suitable edge construction which permits a “soft” leakage of the electrical field in the volume can always be provided over a wide range of concentrations of p and n doping.

Abstract: Dot-pattern-like impurity regions are artificially and locally formed in a channel forming region. The impurity regions restrain the expansion of a drain side depletion layer toward the channel forming region to prevent the short channel effect. The impurity regions allow a channel width W to be substantially fined, and the resultant narrow channel effect releases the lowering of a threshold value voltage which is caused by the short channel effect.

Abstract: A bipolar transistor includes a first layer with a collector. A second layer has a base cutout for a base. A third layer includes a lead for the base. The third layer is formed with an emitter cutout for an emitter. An undercut is formed in the second layer adjoining the base cutout. The base is at least partially located in the undercut. In order to obtain a low transition resistance between the lead and the base, an intermediate layer is provided between the first and the second layer. The intermediate layer is selectively etchable with respect to the second layer. At least in the region of the undercut between the lead and the base, a base connection zone is provided that can be adjusted independent of other production conditions. The intermediate layer is removed in a contact region with the base.

Abstract: A board for connecting a bare semiconductor die with a bond pad arrangement which does not conform to a master printed circuit board with a specific or standardized pin out, connector pad, or lead placement arrangement. The board comprises a printed circuit board including first elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the board and the master board, and second elements, such as minute solder balls, pins, or bond wires, for making electrical contact between the semiconductor die and the board. The board has circuit traces for electrical communication between the board/master board electrical contact elements, and the semiconductor die board electrical contact elements.

Abstract: An organic electro-luminescent display device and a method of fabricating the same are disclosed in the present invention. The organic electro-luminescent display device includes a plurality of pixels on a substrate, a thin film transistor coupled to each pixel, an organic electro-luminescent device coupled to the thin film transistor, a packaging layer on the organic electro-luminescent device, wherein the packaging layer comprises first and second inorganic layers having opposite stresses, and a first organic layer between the first and second inorganic layers.

Abstract: A Schottky diode is adjusted by implanting an implant species by way of a titanium silicide Schottky contact and driving the implant species into the underlying silicon substrate by a rapid anneal. The implant is at a low energy, (e.g. about 10 keV) and at a low dose (e.g. less than about 9E12 atoms per cm2) such that the barrier height is slightly increased and the leakage current reduced without forming pn junction and retaining the peak boron concentration in the titanium silicide layer.

Abstract: A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

Abstract: Apparatus and methods forming electrostatic discharge and electrical overstress protection devices for integrated circuits wherein such devices include shared electrical contact between source regions and between drain regions for more efficient dissipation of an electrostatic discharge. The devices further include contact plugs and contact lands which render the fabrication of the devices less sensitive to alignment constraint in the formation of contacts for the device.

Abstract: A method of fabricating relaxed SiGe buffer layers with low threading dislocation densities on silicon-on-insulator (SOI) substrates is provided. The relaxed SiGe buffer layers are fabricated by the epitaxial deposition of a defect-free Stranski-Krastanov Ge or SiGe islands on a surface of the SOI substrate; the capping and planarizing of the islands with a Si or Si-rich SiGe layer, and the annealing of the structure at elevated temperatures until intermixing and thereby formation of a relaxed SiGe layer on the insulating layer (i.e., buried oxide layer) of the initial SOI wafer is achieved. The present invention is also directed to semiconductor structures, devices and integrated circuits which include at least the relaxed SiGe buffer layer mentioned above.

Abstract: To transfer signal charges at high speed with small noise, there is provided a charge transfer apparatus including a semiconductor substrate of one conductivity type, a charge transfer region of a conductivity type opposite to that of the semiconductor substrate that is formed in the semiconductor substrate and joined to the semiconductor substrate to form a diode, a signal charge input portion which inputs a signal charge to the charge transfer region, a signal charge output portion which accumulates the signal charge transferred from the charge transfer region, and a plurality of independent potential supply terminals which supply a potential gradient to the semiconductor substrate, wherein the signal charge in the charge transfer region is transferred by the potential gradient formed by the plurality of potential supply terminals.

Abstract: The present invention describes a method of manufacturing a semiconductor device, comprising a semiconductor substrate in the shape of a slice, the method comprising the steps of: step 1) selectively applying a pattern of a solids-based dopant source to a first major surface of said semiconducting substrate; step 2) diffusing the dopant atoms from said solids-based dopant source into said substrate by a controlled heat treatment step in a gaseous environment surrounding said semi-conducting substrate, the dopant from said solids-based dopant source diffusing directly into said substrate to form a first diffusion region and, at the same time, diffusing said dopant from said solids-based dopant source indirectly via said gaseous environment into said substrate to form a second diffusion region in at least some areas of said substrate to form a second diffusion region in at least some areas of said substrate not covered by said pattern; and step 3) forming a metal contact pattern substantially in alignment with

Abstract: In aiming at cost lowering of an optical module and an optical transmission apparatus and with the objective of providing a semiconductor light receiving element that has a good coherence with the other edge emitting/incidence type optical devices and is capable of performing the positioning easily and with a high accuracy, in the edge emitting/incidence type light receiving element in which the light absorbing layer 19 has been formed, the space region is formed so as to provide at least 100 &mgr;m2 of the marker detecting region 24, thereby facilitating detection of marker 23 on the optical device 26 and executing the positioning of the light receiving element with a high accuracy, the space region resulting from eliminating a part of the light absorbing layer 19 that absorbs the detection light of the light receiving element, the transmission amount of the detection light toward the marker detecting region that is parallel to a primary plane being equal to 30% or higher, the detection light having penetrat

Abstract: A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive method does not require the use of a solder mask, does not require the melting of the bulk of any of the solder balls and does not require the use of a fluxing agent.

Abstract: A TFT is provided completely separated by an insulating film, in which a parasitic MOSFET is not generated at ends of a semiconductor layer, and the variation in characteristics is small. At least one portion of the ends in the gate-width direction of a gate electrode forming the TFT is disposed in a semiconductor region which forms the TFT, and the ends in the gate-length direction of the gate electrode extend toward the outside of the semiconductor region forming the TFT. With this arrangement, a uniform TFT in which a parasitic MOSFET is not generated at the ends in the gate-width direction is obtainable.

Abstract: A semiconductor device comprises: a semiconductor element; an external terminal used for an external connection; an interposer having the semiconductor element mounted on a first surface thereof and having the external terminal formed on a second surface thereof opposite to the first surface so as to electrically connect the semiconductor element and the external terminal; a resin sealing the semiconductor element on the first surface; and an interconnecting portion formed within the resin, the interconnecting portion having a first connecting part electrically connected to the external terminal and having a second connecting part exposed on an outer surface of the resin.

Abstract: A quantum well made out of a the stack of layers of III-V semiconductor materials comprises, in addition to the quantum well, an electron storage layer separated from the quantum well by a transfer barrier layer. The barrier layer has a thickness that is greater than the thickness of the quantum well by about one order of magnitude. This barrier thus enables the separation of the absorption function (in the quantum well) and the function of reading the photocarriers (in the storage layer) and therefore the limiting of the rate of recombination of the carriers, thus improving the performance characteristics of the detector.

Abstract: There is provided an EEPROM semiconductor device including (a) a plurality of field insulating films each extending perpendicularly to word lines, (b) a plurality of memory cells arranged in a matrix, each memory cell having a floating gate, a control gate formed on the floating gate and doubling as a word line, and source and drain regions located at either sides of the control gate, (c) a common source line extending in parallel with the word lines and connecting source regions of the memory cells with each other, and (d) a first bit line extending perpendicularly to the word lines and connecting drain regions of the memory cells with each other. The above-mentioned EEPROM semiconductor device makes it possible to form CMOS logic circuit together with a non-volatile memory on a common semiconductor substrate without increasing fabrication steps, and also makes it possible for the non-volatile memory to write data thereinto and read data therefrom at a higher rate without an increase in a cell size.

Abstract: An electronic structure bondable to an electronic assembly, such as a chip. The electronic structure may be joined to a electronic assembly, such as a chip, by use of a structural epoxy adhesive. The electronic structure includes a mineral layer on a metallic plate, and an adhesion promoter layer on the mineral layer. The metallic plate includes a metallic substance that includes a pure metal with or without a metal coating. The metallic substance may include such substances as stainless steel, aluminum, titanium, copper, copper coated with nickel, and copper coated with chrome. The mineral layer includes a chemical compound derived from a mineral; e.g., silicon dioxide (SiO2) derived from quartz. Such chemical compounds may include such substances as silicon dioxide, silicon nitride, and silicon carbide. The chemical compound may exist in either crystalline or amorphous form. The adhesion promoter may include such chemical substances as silanes, titanates, zirconates, and aluminates.

Abstract: There is provided a semiconductor device having a COB type DRAM, which comprises a first insulating film formed on a semiconductor substrate, first wiring trenches formed in a first insulating film in the first region, second wiring trenches formed in the first insulating film in the second region to have a substantially same depth as the first wiring trenches, first wirings buried in lower portions of the first wiring trenches, a second insulating film buried in upper portions of the first wiring trenches and formed of material different from the first insulating film, and second wirings formed of same conductive material as the first wirings in the second wiring trenches and formed thicker than the first wirings. Accordingly, the pattern precision of the bit lines and the wirings that have a different film thickness can be increased, and through holes that are formed between the bit lines in the self-alignment manner are formed shallow, and also resistances of the bit lines and the wirings are reduced.

Abstract: An optical semiconductor device includes an optical semiconductor element, a semiconductor region, and a buried layer. The optical semiconductor element is formed on a semiconductor substrate. The semiconductor region opposes the optical semiconductor element and essentially surrounds the optical semiconductor element to form walls. The buried layer is arranged between the walls of the semiconductor region and the optical semiconductor element and formed by vapor phase epitaxy. In this optical semiconductor device, a distance between the wall of the semiconductor region and a side wall of the optical semiconductor element is larger in a portion in which the growth rate of the vapor phase epitaxy in a horizontal direction from the side wall of the optical semiconductor element and the wall of the semiconductor region is higher.