Abstract: A method of making a heterojunction bipolar transistor comprises the steps of: forming a mask layer on a compound semiconductor film by using a photomask for forming an emitter; and forming the emitter by wet-etching the compound semiconductor film by using the mask layer. The photomask has a pattern thereon for forming the emitter. The pattern is defined by a first area R associated with the shape of the emitter to be formed, and a plurality of second areas T1 to T4. Each of the second areas T1 to T4 includes first and second sides S1 and S2 meeting each other to form an acute angle therebetween, and a third side S3 in contact with the first area R. In each of the second areas T1 to T4, one side S3 of the two sides meeting each other to form a right angle therebetween is in contact with one side of the area R, whereas the other side S1 is connected to another side of the first area R to form a line segment.

Abstract: The structure and construction of a bistable twisted nematic liquid crystal display with very long lifetime are disclosed. The two stable twist states in this display when no voltage is applied have almost infinite lifetimes and do not decay. These two stable twist states differ by a twist angle of 180°. New design conditions of this bistable twist structure are disclosed such that the contrast and the brightness are both optimized. This display can be operated in transmittive mode with two polarizes or in the reflective mode with one polarizer.

Abstract: Container structures for use in integrated circuits and methods of their manufacture. The container structures include a bottom conductive layer, a top conductive layer and a dielectric layer interposed between the bottom conductive layer and the top conductive layer. The container structures further include a diffusion barrier layer interposed between the dielectric layer and the bottom conductive layer. The diffusion barrier layer acts to inhibit atomic diffusion to at least a portion of the bottom conductive layer, particularly atomic diffusion of oxygen during formation or annealing of the dielectric layer. The container structures are especially adapted for use as container capacitors. The container capacitors are further adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.

Abstract: Area efficient static memory cells and arrays containing p-n-p-n or n-p-n-p transistors which can be latched-up in a bistable on state. Each transistor memory cell includes a gate which is pulse biased during the write operation to latch-up the cell. Also provided are linked memory cells in which the transistors share common regions.

Abstract: Capacitors and methods of forming capacitors are disclosed. In one implementation, a capacitor comprises a capacitor dielectric layer comprising Ta2O5 formed over a first capacitor electrode. A second capacitor electrode is formed over the Ta2O5 capacitor dielectric layer. Preferably, at least a portion of the second capacitor electrode is formed over and in contact with the Ta2O5 in an oxygen containing environment at a temperature of at least about 175° C. Chemical vapor deposition is one example forming method. The preferred second capacitor electrode comprises a conductive metal oxide. A more preferred second capacitor electrode comprises a conductive silicon comprising layer, over a conductive titanium comprising layer, over a conductive metal oxide layer. A preferred first capacitor electrode comprises a conductively doped Si—Ge alloy. Preferably, a Si3N4 layer is formed over the first capacitor electrode. DRAM cells and methods of forming DRAM cells are disclosed.

Abstract: A method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors is disclosed. Initially a thin layer of silicon is grown on a sapphire substrate. The silicon is improved using double solid phase epitaxy. The silicon is then patterned and implanted with P+-type and N+-type dopants. Subsequently a micrometer scale N-type layer is grown that acts as the intrinsic base for both an PNP transistor and as the collector for an NPN transistor. The extrinsic base for the NPN is then formed and the emitter, collector and ohmic contact regions are next selectively masked and implanted. Conductive metal is then formed between protecting oxide to complete the complementary vertical bipolar junction transistors.

Abstract: A combined transistor and capacitor structure comprising a transistor having alternating source and drain regions formed in a substrate of semiconductor material, and a capacitor formed over the transistor. The capacitor has at least first and second levels of electrically conductive parallel lines arranged in vertical rows, and at least one via connecting the first and second levels of lines in each of the rows, thereby forming a parallel array of vertical capacitor plates. A dielectric material is disposed between the vertical plates of the array. The vertical array of capacitor plates are electrically connected to the alternating source and drain regions of the transistor which form opposing nodes of the capacitor and electrically interdigitate the vertical array of capacitor plates.

Abstract: A method of forming an active area surrounded with an insulating area in a semiconductor substrate, including the steps of forming in the substrate a trench surrounding an active area; filling the trench with an insulating material to form an edge extending beyond the substrate surface at the periphery of the active area; forming a spacer at the periphery of said edge; and implanting a dopant, whereby the implantation in the area located under the spacer is less deep than in the rest of the active area.

Abstract: An object of this invention is to provide a manufacturing process and structure of a thin film transistor having high productivity in which the resistance of a gate electrode wiring line can be decreased, an active layer and source and drain electrodes form an ohmic contact, and the number of masks required in the manufacturing process can be decreased. An amorphous silicon layer and a 1-st gate dielectric layer are consecutively deposited on an insulating substrate by plasma CVD. The 1-st gate dielectric layer is processed together with the amorphous silicon layer into an island shape. A 2-nd gate dielectric layer and a metal interconnection layer are deposited on the 1-st gate dielectric layer. After the metal interconnection layer is etched to form a gate electrode, the 2-nd and 1-st gate dielectric layers are etched to pattern the gate dielectric layer.

Abstract: Transistor and method of manufacturing a bipolar transistor of the double-polysilicon, heterojunction-base type, in which a semiconducting layer with SiGe heterojunction is formed by non-selective epitaxy on an active region of a substrate and an insulating region surrounding the active region. At least one stop layer is formed on the semiconducting layer above a part of the active region. A layer of polysilicon and an upper insulating layer are formed on the semiconducting layer and on a part of the stop layer, leaving an emitter window free. An emitter region is formed by epitaxy in the emitter window, resting partially on the upper insulating layer and in contact with the semiconducting layer.

Abstract: A transistor includes an NPN transistor provided with an N-type emitter, a P-type base, an N-type collector, an emitter diffusion region and a collector compensation diffusion region around the base and the emitter for decreasing a saturation voltage and a parasitic PNP transistor in a region where the NPN transistor is formed, the parasitic PNP transistor operating under saturation of the NPN transistor.

Abstract: A low-cost EMI shield that fits around an integrated circuit package to absorb electromagnetic energy and dissipate it as heat. The shield is not ohmically conductive so it may contact electrically active conductors without affecting the operation of the circuit. EMI is prevented from being radiated by and around an integrated circuit package by a perimeter of material that is lossy to high-frequency electromagnetic currents. This perimeter is fitted around an integrated circuit package such that the gap between a heat sink or other top conductor and the printed circuit board is completely closed by the lossy material. This provides not only a line-of-sight obstruction to RF currents, but also provides a lossy return path to close the circuit loop for currents on the skin of the heat sink. Since the material is lossy, rather than purely conductive, it can be used with a less than perfect ground attachment.

Abstract: The present invention comprises a method for preventing particle formation in a substrate overlying a DARC coating. The method comprises providing a semiconductor construct. A DARC coating is deposited on the construct with a plasma that comprises a silicon-based compound and N2O. The DARC coating is exposed to an atmosphere that effectively prevents a formation of defects in the substrate layer. The exposed DARC coating is overlayed with the substrate.

Abstract: A semiconductor energy detector as disclosed herein is arranged so that an aluminum wiring pattern is formed on the front side of transfer electrodes of a CCD vertical shift register, which pattern includes meander-shaped auxiliary wirings for performing auxiliary application/supplement and additional wirings for performing auxiliary supplement of transfer voltages in a way independent of the auxiliary wirings with respective ones of such wirings being connected to corresponding transfer electrodes to thereby avoid a problem as to lead resistivities at those transfer electrodes made of polycrystalline silicon, thus achieving the intended charge transfer at high speeds with high efficiency.

Abstract: An integrated circuit and method for forming the same. The integrated circuit includes a semiconductor wafer with first and second surfaces. A functional circuit is formed on the first surface of the semiconductor wafer. Further, a metallization layer is formed outwardly from the first surface of the semiconductor wafer. The integrated circuit also includes at least one high aspect ratio via that extends through the layer of semiconductor material. This via provides a connection between a lead and the functional circuit.

Abstract: A SRAM memory cell including an access device formed on a storage device is described. The storage device has at least two stable states that may be used to store information. In operation, the access device is switched ON to allow a signal representing data to be coupled to the storage device. The storage device switches to a state representative of the signal and maintains this state after the access device is switched OFF. When the access device is switched ON, the state of the storage device may be sensed to read the data stored in the storage device. The memory cell may be formed to be unusually compact and has a reduced power supply requirements compared to conventional SRAM memory cells. As a result, a compact and robust SRAM having reduced standby power requirements is realized.

Abstract: A power MOS element includes a drift region with a doping of a first doping type, a channel region with a doping of a second doping type which is complementary to said first doping type and which borders on said channel region and said drift region, and a source region with a doping of said first doping type, said source region bordering on said channel region. Furthermore, said power MOS element includes a plurality of basically parallel gate trenches which extend to said drift region and which comprise an electrically conductive material which is insulated from the transistor region by an insulator. The individual gate trenches are connected by a connecting gate trench, a gate contact only being connected in an electrically conductive way to the active gate trenches via contact holes in said connecting gate trench.

Abstract: A retrograde and periphery well structure for a CMOS imager is disclosed which improves the quantum efficiency and signal-to-noise ratio of the photosensing portion imager. The retrograde well comprises a doped region with a vertically graded dopant concentration that is lowest at the substrate surface, and highest at the bottom of the well. A single retrograde well may have a single pixel sensor cell, multiple pixel sensor cells, or even an entire array of pixel sensor cells formed therein. The highly concentrated region at the bottom of the retrograde well repels signal carriers from the photosensor so that they are not lost to the substrate, and prevents noise carriers from the substrate from diffusing up into the photosensor. The periphery well contains peripheral logic circuitry for the imager. By providing retrograde and peripheral wells, circuitry in each can be optimized. Also disclosed are methods for forming the retrograde and peripheral well.

Abstract: In a gate array having adjacent lines of PFETs and NFETs along a first axis, some gates of PFETs and/or NFETs extend into the region between wells and along a first (x) axis of the lines of transistors to overlap along the axis, so that an extended gate of an nth transistor, a gate of an (n−1)th non-extended transistor and a gate of an (n−1)th non-extended transistor of the opposite polarity lie along an axis (y) perpendicular to the first axis. In a rectangular layout, the upper right transistor (having an extended gate) is connected to the lower left transistor by a short connection along the y axis.

Abstract: A power MOS device that has increased channel width comprises a semiconductor substrate and a doped upper layer of a first conduction type disposed on the substrate. The upper layer comprises a plurality of doped well regions of a second, opposite conduction type and a plurality of heavily doped source regions of the first conduction type at an etched upper surface of the upper layer that comprises parallel corrugations disposed transversely to the source regions. A gate that separates one source region from another comprises an insulating layer and a conductive material. The corrugations provide an increase in width of a channel underlying the gate and the well and source regions.