Abstract: A semiconductor chip having a vertical current conduction structure of a high reliability: a semiconductor device, a circuit substrate, and an electronic apparatus each containing such semiconductor chips; and a method for producing them. A prehole (3) is formed in a silicon substrate (10) surface-oriented to a (100) face by laser beam irradiation. The prehole (3) is enlarged by anisotropic etching to thereby form a through-hole (4). An electrically insulating film is formed on an inner wall of the through-hole (4). An electrically conducting material is provided inside the insulating film to thereby form a metal bump (30).

Abstract: Disclosed is a semiconductor structure and manufacturing process for making an integrated FET and photodetector optical receiver on a semiconductor substrate. A FET is formed by forming at least one p channel in a p-well of the substrate and forming at least one n channel in the p-well of the substrate. A p-i-n photodetector is formed in the substrate by forming at least one p channel in an absorption region of the substrate when forming the at least one p channel in the p well of the FET and forming at least one n channel in the absorption region of the substrate when forming the at least one n channel in the p-well of the FET.

Abstract: The formation of routing traces on an external surface of a semiconductor device, such as a flip-chip, which has a plurality of ball or bump sites patterned in specific locations, wherein the ball or bump sites are in electrical communication with external communication traces which are used to route signals from the flip-chip integrated circuitry. Such external communication traces generally result in unused space on the exterior surface of the flip-chip. This unused space can be utilized for forming routing traces to connect portions of the internal circuitry of the flip-chip rather than forming such routing traces internally, for forming routing traces to connect two or more semiconductor dice, or for forming routing traces for use as repair mechanisms.

Abstract: A method for decreasing the diffusion of dopant atoms in the active region, as well as the interdiffuision of different types of dopant atoms among adjacent doped regions, of optoelectronic devices is disclosed. The method of the present invention employs a plurality of InAlAs and/or InGaAlAs layers to avoid the direct contact between the dopant atoms and the active region, and between the dopant atoms in adjacent blocking structures of optoelectronic devices. A semi-insulating buried ridge structure, as well as a ridge structure, in which the interdiffusion of different types of dopant atoms is suppressed are also disclosed.

Abstract: The present invention relates to multi-layered organic light emitting diode devices having hole-injection and/or hole-transport layers comprising aryl amine compounds with relatively high glass transition temperatures (i.e., thermostable aryl amine compounds). Such multi-layered OLED devices allow for a staircase change in the energy difference of holes and electrons as they migrate from the electrodes toward the emitter layer, resulting in a lower operating voltage and a high quantum yield of luminescence for a given current density. The present invention also relates to microdisplay devices comprising multi-layered organic light emitting diode devices having hole-injection and/or hole-transport layers comprising thermostable aryl amine compounds.

Abstract: A polycrystalline silicon layer is formed on a substrate. An insulating layer and a gate electrode are formed on the polycrystalline silicon layer. Then, a channel region, a source region and a drain region are formed in a self-aligned manner by doping an impurity in the polycrystalline silicon layer using the gate electrode as a mask. Then, an energy absorption layer is formed so as to cover the entire substrate and a pulsed laser beam is irradiated from the energy absorption layer side. The energy of the pulsed laser beam is almost completely absorbed in the energy absorption layer and a heat treatment is indirectly performed on the underlying layers by radiating the heat. In other words, activation of the impurity and removal of defects in the insulating layer are performed at the same time without damaging the substrate by the heat.

Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.

Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.

Abstract: A DRAM array having trench capacitor cells of potentially 4F2 surface area (F being the photolithographic minimum feature width), and a process for fabricating such an array. The array has a cross-point cell layout in which a memory cell is located at the intersection of each bit line and each word line. Each cell in the array has a vertical device such as a transistor, with the source, drain, and channel regions of the transistor being formed from epitaxially grown single crystal silicon. The vertical transistor is formed above the trench capacitor.

Abstract: In one embodiment, the present invention is directed to a method of fabricating a micro-mechanical latching device, comprising: depositing a structural layer in a fabrication plane, wherein the first structural layer possesses a topography; depositing a sacrificial layer adjacent to the first layer such that the sacrificial layer conforms to the topography of the first layer; depositing a second structural layer that conforms to the topography of the first layer; removing the sacrificial layer; and using at least the first structural layer and second structural layer to fabricate the micro-mechanical latching device.

Abstract: An integrated circuit device having an embedded heat slug. The integrated circuit device comprises, in one embodiment, a semiconductor substrate having a frontside surface and a backside surface. The semiconductor substrate includes an integrated circuit on the frontside surface. A heat slug is disposed in an opening in the backside surface of the semiconductor substrate adjacent the integrated circuit.

Abstract: The invention relates to an SOI substrate which is provided with a recess that cuts through the silicon layer and the SiO2 layer (O). An upper part of said recess (V) which is located in the range of the silicon layer (S) has cylindrical shape with a horizontal first cross-section. A lower part of the recess (V) which is located in the range of the SiO2 layer (O), compared with the upper part of the recess (V), is bulged to such an extent that it has a cylindrical shape with a horizontal second cross-section that is larger than the first cross-section. A cylinder (Z) of an insulating material is provided in the recess (V). The horizontal cross-section of said cylinder corresponds to the first cross-section and the lower part thereof is located in the lower part of the recess (V). The dent laterally surrounds the lower part of the cylinder (Z).

Abstract: A structure is provided which suppresses a parasitic bipolar effect without decreasing the breakdown voltage at the junctions between the excessive carrier extracting region and source/drain regions of a MOS transistor for a voltage of approximately 15 volts in a semiconductor device formed on a semiconductor layer on an insulating layer. In the MOS transistor having a source tied body structure, a semiconductor regions having a low impurity concentration is formed between a regions for extracting excessive carriers and source/drain regions. Thus, the breakdown voltage at the junctions between the extracting regions and the source/drain regions is increased and a parasitic bipolar effect is suppressed without breakdown between the extracting regions and the source/drain regions.

Abstract: The present invention relates to a reverse conducting thyristor device. It aims at preventing heat generated by power loss from filling end field protective rubber and at simplifying a sheath storing a semiconductor substrate. In a reverse conducting thyristor device according to this invention, a self-extinguishing thyristor region is arranged on an inner region of the semiconductor substrate, a reverse conducting diode region whose outer periphery is completely enclosed with an isolation region is arranged on its outer region by at least one, and an external takeout gate electrode region is further arranged on the outermost peripheral region of the semiconductor substrate on the outer part thereof. Thus, a gate electrode provided on a surface of a gate part layer of the self-extinguishing thyristor region is connected with an external takeout gate electrode formed along the outermost periphery of the substrate through a gate wiring pattern formed on a surface of a connecting region.

Abstract: A simplified process for flip-chip attachment of a chip to a substrate is provided by pre-coating the chip with an encapsulant underfill material having separate discrete solder columns therein to eliminate the conventional capillary flow underfill process. Such a structure permits incorporation of remeltable layers for rework, test, or repair. It also allows incorporation of electrical redistribution layers. In one aspect, the chip and pre-coated encapsulant are placed at an angle to the substrate and brought into contact with the pre-coated substrate, then the chip and pre-coated encapsulant are pivoted about the first point of contact, expelling any gas therebetween until the solder bumps on the chip are fully in contact with the substrate. There is also provided a flip-chip configuration having a complaint solder/flexible encapsulant understructure that deforms generally laterally with the substrate as the substrate undergoes expansion or contraction.

Abstract: An EEPROM memory cell integrated in a semiconductor substrate comprises a floating gate MOS transistor having a source region, a drain region, and a gate region projecting from the substrate and is isolated from the substrate by an oxide layer including a thinner tunnel portion and heavily doped regions formed under said tunnel portion and extending to beneath the drain region, and a selection transistor having a source region, a drain region and a gate region, wherein said source region is heavily doped and formed simultaneously with said heavily doped regions.

Abstract: A method is proposed for fabricating a TFBGA (Thin & Fine Ball-Grid Array) package with embedded heat spreader. Conventionally, since an individual TFBGA package is quite small in size, it would be highly difficult to incorporate an embedded heat spreader therein. As a solution to this problem, the proposed method utilizes a single substrate pre-defined with a plurality of package sites, and further utilizes a heat-spreader frame including an integrally-formed matrix of heat spreaders each corresponding to one of the package sites on the substrate. A batch of semiconductor chips are then mounted on the respective package sites on the substrate. During the encapsulation process, a single continuous encapsulation body is formed to encapsulate the entire heat-spreader frame and all the semi-conductor chips. After ball implantation, a singulation process is performed to cut apart the encapsulation body into individual package units, each serving as the intended TFBGA package.

Abstract: Chip stack type semiconductor package and method for fabricating the same, the package including a lower chip having a center pad formation surface defined at a bottom thereof, an upper chip stacked on the lower chip by being adhered to a top surface of the lower chip having no center pad formed thereon and having a center pad formation surface defined at a top surface thereof, both surface adhesive insulating tapes attached on regions spaced from, and positioned left and right sides of respective center pads formed in the center pad formation surfaces of the lower chip and the upper chip, leads having inner lead portions inside of a molded body of an encapsulation resin and outer lead portions exposed outside of the molded body and both end portions of the leads attached to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the upper chip and to the both surface adhesive insulating tapes attached on left and right sides of the center pads of the lower chip oppos

Abstract: This invention comprises an improved method of planarizing, an integrated circuit formed onto a semiconductor substrate and the planarized semiconductor substrate. Improved planarity is accomplished through the use a first and second stop layer separated by a filler layer. A first stop layer is used to define active and trench regions. A filler layer is then applied over the surface of the substrate and a second stop layer is applied on top of the filler layer. The second stop layer is patterned through etching. The pattern etched into the second stop layer is used to control chemical mechanical polishing that planarizes the surface. Patterns can be a reverse image of an active mask or a continuous pattern. In addition CMP can be used to create a condition of equilibrium planarity before the second stop layer is applied. The stop layers can comprise polysilicon, silicon nitride, or another material that is harder than a dielectric oxide material used as filler material.

Abstract: The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having annular floating gates. The present invention uses the capacitance coupling between the source and the floating gate to form a channel in the substrate under the floating gate. Hot electrons are injected into the floating gate or released from the floating gate to the control gate through inerpoly dieletric by injection point on the top of floating gate In the proposed memory cell, a floating gate is etched to form an annular shape situated between a drain, a source, and two field oxides. An interpoly dielectric and a control gate are stacked in turn on the floating gate and on the surface of the substrate not covered by the floating gate through means of self-alignment. An injection point not covered by the SiN film of the interpoly dielectric is formed on the top of the floating gate.