Abstract: A speech recognition system includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache.

Abstract: Improved performance is obtained in computers of the type having vector registers which communicate with one or more functional units and common memory. As elements of a vector are read from a vector register for transmission to common memory or as operands to a functional unit, the vector register immediately becomes available to receive and store elements of a vector from common memory or a functional unit. The element-by-element storing takes place simultaneously with the element-by-element reading, and trails the reading by at least one element so as to not overwrite elements yet to be read. Through the use of this technique a vector register can be loaded with a vector for a subsequent operation without having to wait for the completion of the previous operation which uses the same vector register.

Abstract: A method and apparatus for providing an historical perspective into a database of information objects through an efficient method and apparatus for versioning information objects stored in a database as well as an index representative of the information objects is disclosed. The latest versions of each one of the information objects and each one of the entries in the index are maintained in the database. Partial earlier versions of each one of the information objects and each one of the index entries are stored with the latest versions. The partial versions contain only sufficient information about the differences between the earlier versions and the later ones so that any earlier version may be reconstructed. Identification tags are employed as unique identifiers for each one of the plurality of information objects and for different versions of the information objects.

Abstract: A processing unit tightly couples to a system bus and includes a local memory which is accessible from such bus. The processing unit includes a high performance microprocessor which tightly couples to the local memory through a high speed synchronous bus shared with a plurality of synchronous state machines. A microprocessor internal bus state machine and the plurality of state machines control local bus accesses for transferring commands generated by the microprocessor and commands transferred from the system bus under the control of an external state machine for execution by a local memory state machine and the processor state machine, respectively, which also couples to the system bus.

Abstract: An operator MUX interface (OMI) (102) includes a data base manager (203) that manages at least two data bases. The first comprises a substantially non-temporary data base, and the second comprises a substantially temporary data base. The latter includes information from both the first data base, and other information as well. The data base manager (203) automatically alters the data storage structure of the second data base whenever either the data storage structure for the first data base is changed, or whenever new information must be added to the second data base, and the data storage structure of the second data base will not readily accommodate that addition.

Abstract: A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.

Abstract: Another object is to enable different types of control instructions to coexist, wherein an address converter table is used to rapidly shift addresses in a memory without adversely affecting other operations. A method of controlling a manufacturing line using a central processing unit, wherein the various addresses in a memory are rapidly shifted using an address converter table so that different types of control instructions, such as compiler and interpreter languages, can coexist without any adverse affects. The method enables utilization of a high speed CPU and low speed I/O devices.

Abstract: This invention includes an apparatus for storing image data associated with related title data in a storage medium. The invention includes a scanner for reading image data (bit map image data), a combining unit for combining verification data (character data) with the image data read by the scanner, an optical disk for storing the verification data and the image data, a magnetic disk for storing search data, a keyboard or mouse for designating specific data of the search data stored in the magnetic disk, a read unit for reading out the image data and the verification data stored in the optical disk, and control unit for, when the verification data read out by the read unit and the search data designated by the keyboard or mouse match, for storing the search data in the optical disk together with the image data.

Abstract: To increase the kinds of executable instructions of a microcomputer without increasing the number of bits (e.g. 8 bits) constituting one word or instruction, that is, without decreasing the execution speed or increasing the ROM usage, two or more instruction groups including instructions of different kinds, respectively, are provided operation modes are determined for the respective instruction groups; and the respective instruction groups to be executed are switched according to the respective operation modes. The microcomputer includes an instruction register, an execution control unit, a mode memory flip-flop, gates, two predecoders, a programmable logic array, an arithmetic logic unit, etc. The ordinary and special instruction groups can be selected in response to an interrupt entry signal and an interrupt return signal and a specific bit of an instruction, for instance.

Abstract: In an instruction processing unit of an information processing system in which operable instructions are executed as executing instructions on operands held by operand registers to store results of execution in result registers and in which a bypass arrangement is controlled by an enable signal to bypass the operand and the result registers when an instruction is one of inoperable instructions and should use, as a particular operand, a particular result of execution of a particular one of the executing instructions, an instruction managing section (52) manages the execution instructions by entry numbers related individually to the executing instructions to successively produce the entry numbers as managed entry numbers at predetermined time instants.

Abstract: A database system includes a database unit for storing a database, a managing processor and a processor. The managing processor manages the database unit and accesses the database unit in response to an inputted particular request. The processor internally generates a request in accordance with a user program, directly accesses the database unit in accordance with the generated request when the generated request is one of first predetermined requests, and outputs the generated request to the managing processor as a particular request when the generated request is one of second predetermined requests. Each of the second predetermined requests incurs a change in contents of the database, and the managing processor updates a log stored in a log unit in accordance with processing for the particular request.

Abstract: A processor for collecting boolean conditions of multiple operations includes a condition collection register which may be written and read in parallel or written serially and into which a single bit is shifted from either the left or the right, and a processor instruction decoder that decodes one operand register addresses as a read address for the condition collection register, and three operand register addresses as a write address for said condition collection register.

Abstract: An apparatus for supporting development of a graphic data driven program includes a data driven mechanism enabling instructions of the data driven program to be executed whenever all input data necessary for executing the instructions is available.

Abstract: A peripheral mass memory subsystem (PSS.sub.1, PSS.sub.2) of an information processing system including at least one central host (H.sub.1, H.sub.2, H.sub.4, H.sub.4), two control units (UC.sub.1, UC.sub.2) and at least one mass memory (BMD.sub.1, BMD.sub.2, . . . ,) with independent electrical power supplies (ALIM.sub.1, ALIM.sub.2, BAT.sub.1, BAT.sub.2) and each having a plurality of structural (hardware+microsoftware) elements (PR.sub.1 -PR.sub.2, DE.sub.1 -DE.sub.2, CA.sub.1 -CA.sub.2, HA.sub.1 -HA.sub.2, DA.sub.1 -D.sub.2) connected to a first and/or a second parallel-type bus (B.sub.1, B.sub.2). The subsystem is characterized in that it includes a microsoftware architecture (AML) that executes the commands of the host and informs the host of changes in state of the mass memory and is embodied by a plurality of functional microsoftware subassemblies (P, H, D, C, S), each of them specific to each structural element of each control unit and implemented in its hardware structure.

Abstract: An electromechanical apparatus includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: A system for registering and calling documents in a character processing unit includes a memory for storing character string information and title information associated with the character string information, and a display for displaying the title information stored in the memory. An entry device enters the title information and a call device calls the relevant character string information from the memory by entering the title information associated with the title information displayed on the display from the entray device. A registration device registers a new character string by entering the title information which is not stored in the memory device and reads out a character string which is stored in the memory device.

Abstract: A system is provided for enhancing a compiler with the capability to install a fastpath within a compiled program. The enhanced compiler allows a program to use the benefits of a fastpath without requiring the addition of new code to the source code. Any type of program, including multi-media, can benefit from the enhanced compiler. A program need only be evaluated to see if there are functions/procedures which can utilize a fastpath. A programmer may turn the enhancement on or off depending upon whether or not there are recurring calculations with results that do not change over time from the same input.

Abstract: A modem includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: The sorting and merging of unordered input signals is widely used in all types of information and communication circuits and methodologies. A sorting network is provided by providing a modified Batcher network. The network is recursively built up from a size 4 network to an arbitrary size. The modified Batcher network sorts N data items in log.sub.2 N passes through the network, where N is the number of data items in each series. The network has a delay of log.sub.2 N with comparators of log.sub.2 N different lengths with a maximum length of N/2.