Abstract: An apparatus for estimating the solution to a finite element analysis and/or regularization equation, the apparatus including means for generating a pyramid representation of input data, each level of the pyramid representation corresponding to a different set of similar eigenvectors; means for multiplying at least one of the levels of the representation by a weight derived from the eigenvalue associated with the set of eigenvectors for that level to generate a weighted pyramid representation; and means for collapsing the weighted pyramid representation to generate an estimated solution to the equation.

Abstract: A design supporting method having a specification edit function in an information processing system having a computer and an interactive terminal is disclosed. Items to be described in a specification are correlated among specifications so that when an item described in the specification is modified, a portion which is possibly affected by the modification can be analyzed.

Abstract: A computer storage register architecture permitting secure atomic access to set or clear one or more particular bits wherein a multiple bit register is disclosed. In the preferred embodiment, a multiplicity of unique addresses is assigned to a multiple bit register. One address constitutes a read address, one address constitutes a clear address, and a third address constitutes a set address. An address decoder decodes the addresses assigned to the register so that only that register is accessed for the associated read, clear, and set operations, respectively. Data having a register position equivalent binary pattern of logical zeros and ones corresponding to particular bit locations of the register to be set or cleared are associated with the set and clear addresses. If the position equivalent binary value of the data associated with the address decoded is a logical one, then the corresponding bit in the register will be set or cleared. Otherwise, the bit remains unchanged.

Abstract: An apparatus for performing storage and retrieval in an information storage system is disclosed which uses the hashing technique. In order to provide efficient and graceful operation under varying loading conditions, the system shifts between collision avoidance by linear probing with open addressing when the load is below a threshold, and collision avoidance by external chaining when the load is above a threshold. Insertion, deletion and retrieval operations are arranged to switch dynamically between the two collision avoidance stratagems as the local loading factor on the system, as measured by the number of records hashed to the same address, crosses preselected thresholds.

Abstract: Method and computer database system for implementing an interactive prompted query system in a database system having a plurality of named database tables which a user can link together for query purposes by entering join statements. The join statements are analyzed by determining that one or more groups of separately linked database table names are referenced in the join statements. If more than one group exists, then the join statements are adjusted so that only a single group of separately linked database table names is referenced by the join statements. The single group of names may be determined by selecting the group which contains the name first entered by the user, by selecting the group which contains the highest number of names, by prompting the user to select the group or by any other logical means. More particularly, the join statements are analyzed using a graphical technique to determine the groups of tables.

Abstract: A word processor for setting a format of a text, having a format controller for controlling a newly set format to be effective from the beginning of a character data group to which the position where the format setting operation is carried out belongs, and a reformatter for reforming at least the character data group based upon the newly set format. The word processor searches backward and forward in the text for locating line feed codes designating the beginning and end of the character data group, respectively, and selects the beginning and end of the text when the line feed codes could not be located.

Abstract: The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detected, are removed altogether from the pipeline, but still processed. The processing is synchronized with the execution pipeline to, first, predict an outcome for detected branch instructions, second, test the conditions for branch instructions at their proper place in the execution sequence to determine whether the predicted outcome was correct, and third, fetch a corrected target instruction if the prediction proves wrong.

Abstract: A semi-dynamic load balancer for a transaction processing system reallocates transaction types among computers in the system as a group rather than as individual transactions. Statistical data is accumulated in an affinity matrix which records the number of times a transaction type i was blocked by transaction type j was holding a lock on a data item that transaction type i wanted to access. When an overloaded computer is detected, transaction types are reallocated on the computers of the system according to a transaction type routing table which is updated based on data from the affinity matrix.

Abstract: Method and apparatus for detecting infinite tight loops and infinite inter-task loops in applications tasks in multi-task, real-time systems. In accordance with the inventive method, a low priority task, the idle task, is executed whenever no other task is ready to execute. Further, when the idle task executes it sets a flag. A higher priority, watch dog task executes and tests the flag. If the flag has been set, the watch dog task resets the flag and sends a signal to reset a watch dog timer, however, if the flag has not been set by the idle task for a predetermined time period, the watch dog task will stop resetting the watch dog timer. As a result, this will cause the watch dog timer to trigger and reset the system.

Abstract: A method and computer system having a processor are provided for selectively compressing a data communication frame for data transfer between the computer system and at least one other system. A processor work load is periodically identified for the processor. A predetermined stored threshold value is identified and compared with the identified processor work load. Responsive to an identified processor work load greater than the identified predetermined threshold value, the data communication frame is transmitted without compressing the data communication frame. Otherwise the data communication frame is compressed and then transmitted responsive to an identified processor work load less than or equal to the identified predetermined threshold value. A state of a communication line is identified for the data transfer. Responsive to an identified idle state of the communication line, the data communication frame is transmitted without compressing the data communication frame.

Abstract: In the present invention a digital communication controller for interfacing with a master processor and a synchronous bus having a plurality of slave processors connected thereto is disclosed. The digital communication controller provides synchronous transfer of instruction and data in each microcycle to the bus. However, the data provided in each microcycle is multiplexed such that it is associated with the instruction transmitted previously but not contiguous in time therewith.

Abstract: A method and apparatus for performing a fast jump address calculation is disclosed. A field from the instruction is provided to an adder, on the assumption that it is the displacement value, without actually determining whether it is a displacement value. A fixed instruction length is also provided to the adder, on the assumption that the instruction will have that length. Finally, the current instruction address bits from the program counter are provided to the adder. These are added together to provide a jump address.

Abstract: Mass data is managed as data files in a mass data storage device. Each data file is formed or plural data blocks. Upon editing of a data file, the data content of each data block forming the file is examined. If the data content of a data block is less than a predetermined value, data from one or more adjacent data blocks is extracted and placed in the one data block so that the data content thereof will be at least the predetermined constant value. In this manner, the data content of blocks forming a file is maintained at or above a predetermined level.

Abstract: A multiprocessor system intercouples the processors with an active logic network having a plurality of priority determining nodes. Messages applied concurrently to the network in groups are sorted, using the data content of the messages, to a single or common priority message which is distributed to all the processors with a predetermined total network delay time. Losing messages are again retried concurrently in groups at a later time. Message routing is determined by local acceptance or rejection of messages at the processors, based upon destination data in the messages. All messages occupy places in a coherent priority scheme and are transferred in contending groups with prioritization on the network. Using data, status, control and response messages, and different multiprocessor modes, the system is particularly suited for configuration in a relational data base machine having capability for maintaining an extended data base and handling complex queries.

Abstract: A memory cartridge having a case and a printed circuit board housed in the case connected, in use to a data processing unit including a microprocessor and a picture processing unit. A memory cooperating with the data processing unit is installed on the printed circuit board, and an area of the memory is divided into a plurality of banks. A multi-memory controller installed on the printed circuit board includes a plurality of registers into which microprocessing generated data, representing bank switching conditions, are loaded. An address for switching the memory banks is output in response to the content of at least one of a plurality of registers. Thus, by changing the above-described data, the microprocessor can specify a specific bank at a specific time and utilize that bank.

Abstract: A microprocessor having two different modes of operation includes a mode flag which designates one of the two operation modes of the microprocessor, and a central processing unit which executes a program in one of the two operation modes designated by the mode flag. The central processing unit includes a microprogram memory which stores an interrupt initiation microprogram, an output device which is responsive to an interrupt request for reading out the interrupt initiation microprogram from the microprogram memory and a circuit for executing the interrupt initiation microprogram to generate a sampling signal. A mode terminal is provided, which is supplied with operation mode information. A circuit responsive to the sampling signal samples a logic level of the operation mode information at the mode terminal. A circuit is provided, which is responsive to the sampled logic level from the sampling circuit in order to bring the mode flag into one of set and reset states of the mode flag designation.

Abstract: An interface unit which can reduce the hardware cost by interfacing a microprocessor with an inexpensive memory device with a smaller word size without compromising the overall performance. The current invention improves the overall performance of the interface system by reducing the overhead address relatching without adding expensive and sophisticated pieces of hardware. This is accomplished by comparing a row address portion of the current address with that of the previous address. When a current address contains the same row address as the previously accessed memory-page, the current invention saves clock cycles by avoiding relatching of the row address portion of the address in the memory device. Such saving is significant when contiguous addresses are sequentially accessed.

Abstract: A byte swapping circuit which selectively orders the bytes of a 16 or 32 bit word to enable proper transmission of data between an AT computer and a VMEbus. The byte swapping circuit generally includes first, second, third and fourth groups of buffers which are disposed in parallel along an internal bus of the circuit. The first group of buffers swaps the bytes of a word having bytes A, B, C and D into the order D, C, B and A. The second group of buffers transmits a word having bytes A, B, C and D in the same order without any byte swapping. The third group of buffers swaps the bytes A and B of a 16 bit word into the order B, A. The fourth group of buffers shifts the C and D bytes of a 32 bit word, which would normally occupy bit positions 16-31, into bit positions 0-15. A control register selectively enables one group of buffers at a time to effect the needed byte swapping.

Abstract: An output driver and method including an output pad, for performing write operations from a central processor unit to a cache memory. The driver includes a pull-up circuit electrically connected to the output pad for switching the pad to a first logic state and a pull-down circuit electrically connected to the output pad for switching it to a second logic state. A plurality of signals are input to the pull-up and pull-down circuits to perform the switching of the output pad at integer and integer and a half clock cycles.

Abstract: In a computer system, an arrangement for storing condition signals indicative of the position of a pointing device and the condition of a button thereof, apparatus for comparing present condition signals generated by a pointing device with stored signals indicative of a previous condition of the pointing device, and apparatus responsive to the comparison of present condition signals generated by a pointing device for generating a pointer interrupt signal only if a change in the pointer condition has occurred.