Abstract: A sequential prefetch method is provided for a pipelined data processor having a sequential instruction prefetch unit (IPU). An instruction queue in the IPU is coupled to a pipelined instruction unit and an instruction cache of the data processor. A prefetch controller in the IPU keeps the instruction stream prefetched so that the instruction queue may load any combination of one, two, or three word instructions into the pipelined instruction unit every clock cycle. The pipelined instruction unit receives instruction words from the instruction queue, and decodes the instruction for execution operations, and for the instruction length/pipeline movement. A queue filling method is provided for maintaining the requisite number of instruction words in the instruction queue to avoid pipeline stalls. The queue filling method is based upon the movement of the instruction pipeline attributable to the usage by an instruction sequencer of the instruction words received from the instruction queue.

Abstract: A method for verifying the conformance of an application program to a set of system rules characterized by the development of a conformance database, the performance of a static analysis of the application program to determine whether the application program is in static conformance with the conformance database and the performance of a dynamic analysis of the application program to determine whether the application program is in dynamic conformance with the conformance database. The static analysis produces a graph of the basic blocks of the application program and analyzes the graph for conformance to system rules, dead code and coverage metrics. The dynamic analysis adds a small amount of monitoring code into an executable application program which monitors the application program as it is exercised in a test harness. The monitoring code produces a log database which can be analyzed for run-time non-conformities of the application program.

Abstract: A signal processing apparatus includes an electronic processor responsive to a context signal and operable in alternative processing contexts identified by the context signal. First and second registers are connected to the electronic processor to participate in one processing context while retaining information from another processing context until a return thereto. A context switching circuit is connected to the first and second registers and operates to selectively control input and output operations of the registers to and from the electronic processor depending on the processing context. Other devices, systems and methods are also disclosed.

Abstract: In a computer system capable of being configured in a multiprocessor system, a plurality of virtual machines are grouped by object of use to define a plurality of processor groups. Each processor has an identifier for a processor group to which it belongs. When an instruction which requires synchronous execution among the processors is executed, the processor identifies the processor group to which it belongs and requests the synchronous execution of the instruction to only the processors in the group. In another aspect, each processor which has a request for execution refers to its own identifier to determine if the request is from a processor of the same group in order to determine whether it should execute the instruction or not. When the processor completes the execution of the instruction, it sends an end signal to the requesting processor so that another instruction from other processors in the same group can be executed.

Abstract: A computer interface having time frame dependent functional designation of parallel port lines system. A communication cycle is established with a plurality of time frames for a group of parallel port lines. Discrete data bytes are transferred to and from a computer, during at least one of the time frames and data blocks are transferred, to and from the computer, during at least one other of the time frames. The designation of the parallel port lines is redefined during each of the time frames to accommodate the transfers to and from the computer of the discrete data bytes and data blocks. Discrete data bytes and data blocks to be sent and received are stored and this storing is conditioned as a function of the designation of the parallel port lines during each of the time frames.

Abstract: A system for processing code contained in one or more selected files, before the code is linked to form an executable image, determines the locations in memory where the code will be stored after it is linked, and revises the code to correspond to the determined memory locations. The object code files include code comprising a programming environment, such as LISP, and code input by a user. The user can delete selected portions of the programming environment. Read only, static, and dynamic memory are utilized and each portion of the code input by the user is evaluated to determine which memory is most appropriate.

Abstract: A sorting arrangement such as in a pattern recognizer employs a memory having N data storage locations. The same extreme value data signal is initially placed in each location. The memory locations are partitioned into two or more sections. A sequence of input signals having values other than the extreme value are received. The value of the current input signal is compared to the values of the data signals in the first section to determine a position for the input signal among the memory locations while, concurrently, the immediately preceding input signal is compared to the values of the data signals of the second section to determine a position for the immediately preceding input signal in the memory locations. The sorting is speeded up by the input signal overlap.

Abstract: This invention relates to a personal computer having facility for ready variation in the amount of memory capability available on the microprocessor local bus. The personal computer has a microprocessor, a high speed local bus coupled to said microprocessor, a system bus, a bus controller coupled to and providing communication between the local bus and system bus, and a local bus memory facility coupled to and physically separable from the local bus. The local bus memory facility is provided by a substrate, preferably a printed circuit card, for mounting and providing coupling connections among components mounted thereon, at least one volatile memory component mounted on the card, and a memory controller mounted on the card and coupled to the volatile memory component, local bus and bus controller, with the memory controller regulating communications between the volatile memory component and microprocessor.

Abstract: Contention handling apparatus which receives access request signals from a number of users and processes these requests to allow controlled access to a shared resource. The contention handling apparatus includes a number of access blocks, with one of the access blocks being associated with each user. A busy line of each of the access blocks is connected to receive a busy signal; the busy signal being an access request signal from a higher priority user, thereby indicating that the shared resource is unavailable. Each access block receiving a busy signal, latches the corresponding access request signal until the busy signal is deasserted. If the busy signal and the access request signal occur at the same time, the corresponding access block generates a wait output signal. The logical sum of the wait output of an access block associated with a next higher priority user and the access request signals of all the higher priority users serves as the busy signal for one of the access blocks.

Abstract: A parallel processing computer system for solving a system of linear equations having coefficients residing in a first matrix and right-hand sides of the linear equations residing in a first vector. The first matrix is divided into a plurality of ND row disk sections, a plurality of ND column disk sections and ND diagonal disk sections. Each of these sections, in a preferred embodiment, are known as disk sections, and are stored on non-volatile media such as magnetic and/or optical disks. Further, the equations are defined by the first vector, the first vector comprising ND sections. Each of the plurality of j row sections and j column sections is factored. Then, the j diagonal section is factored and inverted. In a preferred embodiment, the inversion uses a Gauss-Jordan technique. These steps are repeated for all values of j that range between 1 and ND.

Abstract: A parallel computer architecture incorporates a new register file organization for parallel ALUs that provides improved performance due to reduced off-chip crossings and locally higher density. Each ALU is provided with its own, smaller register file located on the ALU chip. Data written by one ALU is "broadcast" to all the "local" register files. This arrangement of "local" register files minimizes the number of pins required and, using very large scale integration (VLSI) techniques, high densities can be achieved. These "local" register files eliminate off-chip delays, and performance is further enhanced by the shorter wire lengths in the local register files.

Abstract: A semiconductor integrated circuit comprises a plurality of bus line means for transferring data, a plurality of bus line driving means, connected to the bus line means and including one or more FETs, for determining a logical level of the bus line means, and a ground potential wire connected to the bus line driving means and arranged parallel to the bus line means.

Abstract: Conventional microprocessors await the data on the bus for acceptance for a given number of processor clock signals after accessing an external device, notably after a read instruction for an external data memory. When a comparatively slow memory is used in conjunction with a fast microprocessor, it may occur that the data is not yet present at the anticipated instant. In microprocessors in which no hold state is provided it is known to reduce the clock frequency during the reading of the external memory until the data is actually available. However, this results in a fluctuating mean clock frequency of the microprocessor so that internal timing members, controlled by the clock, cannot determine defined periods of time. In accordance with the invention, the clock frequency is reduced during the part of the operating cycle of the microprocessor during which an external device can be accessed, the microprocessor operating at the maximum clock frequency during the remainder of the cycle.

Abstract: Improved database structure is described in which the fields of each database record are divided into two classes, navigational and informational data. The data in the navigational fields is stored in a topological map which may be viewed as a tree structure or the merger of two or more such tree structures. The informational data is preferably stored in a conventional relational database. Each leaf node in the topological map specifies a unique record in the relational database.

Abstract: A computer system with a number of subsystems or modules on separate circuit boards employs electronic keying to ensure proper configuration of these boards. A power key arrangement associated with a plug-in connector enables a separate power supply for each set of boards. A power supply turn-on signal is routed through a uniquely-configured connector path for each board, so the power supply turn-on is inhibited for improper configurations. The uniquely-configured connector path may use either a series or a parallel implementation. The series implementation employs a set of diodes connected for conduction in either of two directions, with the mating connector having its conductor paths connected to match the diode configuration; in this manner, the power supply enable signal can only flow through the series path if the proper board is plugged into a properly-coded slot, in which case the power supply to activate this board is activated through the series path including the diodes.

Abstract: A spreadsheet program providing the combination of spreadsheet and database tools, and enabling users to develop an application environment that can use all resources in the spreadsheet storage area. The spreadsheet program comprises three storage areas: a spreadsheet data structure; a set of database files in a storage area, and a video display system. The spreadsheet data structure is divided into two sets of cells that can be operated through three different environments. The first environment contains the tools of a spreadsheet environment, and the first set of cells can be operated through the first environment. This is most appropriate for scratchpad uses. The second environment contains the tools of a spreadsheet environment and contains a special command that can define commands for the third environment. This is appropriate to develop formulas for an application, and the application's environment of operation.

Abstract: A sequencer controller for nuclear magnetic resonance imaging includes a level-sensitive external gating arrangement. When a sequencer microcode WAIT instruction is executed, the gating arrangement operates differently depending on the level of the signal existing at the external gating input. If the external gating signal level is at one level, the gating arrangement causes the sequencer to wait until the external gating input changes level--thus permitting an external gating event (e.g., closure of a breath switch or the like) to interact with and control the timing of the NMR sequence. If the external gating signal is at a different level when the WAIT instruction is first executed, however, the sequencer does not "wait" at all but instead ignores the WAIT instruction and goes to the next sequencer state.

Abstract: An electronic filing apparatus files documents employing an optically readable mark sheet. A scanner reads a set of data sheets including the mark sheet and original sheets. The mark sheet sets reading conditions for scanning the original sheets in the scanner according to marks on the mark sheet. Original image data on the original sheets is read based on the set reading conditions and filed in a storage device. For filing small amounts of information, both control mark and original image information may be included on a single sheet. The mark sheet may include marks representing search terms descriptive of the content of the original image data which can be used by an operator to search the electronically registered and filed documents.

Abstract: A computer system with self-describing feature table, accessible by device drivers. Thus a simple process can access these feature tables to fully customize the device drivers at installation, or at boot; or the device driver can branch on the data in the feature table. Thus, a new degree of flexibility is achieved without degrading performance.

Abstract: A tree sorter having hardware logic node registers and output selectors plus comparators enables a vector processor to perform sort and merge operations. A system and method of providing one output record each cycle provides performance enhancement over similar scalar operation. Storage to storage traffic is drastically reduced because the hardware tree and update logic is implemented in the Vector Processor. Vector registers provide input data to the hardware tree structure. Output records sorted by key together with address ID are placed in storage. Multiple Vector count and multiple Vector Interruption Index (VIX) operation, string length and merge masks are used in conjunction with a vector merge instruction. The data input record key field has both long and short formats. Actual key data or codewords may be used. The vector merge forms a new codeword when compare equal codewords are encountered.