Abstract: An architecture for a single chip dynamic video random access memory using a single clock to operate the random port to perform refresh, memory address, and to control the internal circuitry for inputting data and addresses and for outputting data as well as modifying information in the memory circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information in the RAM and further having the write masking circuitry for modifying selected portions of the line of stored video information between selected START and STOP bit locations within the like.

Abstract: A semiconductor chip for processing or storing information and a system comprising a plurality of semiconductor chips for processing or storing information. In one form of the invention each chip includes clock input and output circuitry for receiving and transmitting signals of a first frequency and transmission circuitry for receiving and transmitting data. The transmission circuitry is capable of sampling the data at a second clock frequency which is less than the first clock frequency. Circuit components are coupled to the clock circuitry and transmission circuitry for processing the data. In another form of the invention a semiconductor chip comprising clock input and output circuitry, transmission circuitry and circuit components for processing data further includes input circuitry for selecting a variable delay between the time data is received onto the chip and transmitted from the chipIn a preferred embodiment of the invention the semiconductor chip includes a memory array for storing data.

Abstract: An object based operating system for a multitasking computer system provides objects which represent the architecture or interrelationships of the system's resources. Access to certain objects is required in order to use corresponding resources in the system. All objects have a consistent data structure, and a consistent method of defining the operations which apply to each type of object. As a result, it is relatively easy to add new types of system objects to the operating system. The object based operating system supports multiple levels of visibility, allowing objects to be operated on only by processes with the object's range of visibility. This allows objects to be made private to a process, shared by all processes within a job, or visible to all processes within the system. An object or an entire set of objects can be moved to a higher visibility level when objects need to be shared.

Abstract: In an operating system generation method of a computer, a symbolic name is converted into an identification code, which is further converted into an address. This enables an inter-reference operation to be achieved between a kernel and input/output device drivers, thereby independently generating the input/output device drivers and the kernel. As a result, depending on the hardware configuration of the user system, input/output device drivers can be incorporated into the operating system.

Abstract: A virtual lookaside faclity is provided for maintaining named data objects in class-related data spaces in virtual storage, readily retrievable by user programs. A search order is associated with each user, specifying an ordered list of "major names" which are, in effect, sequentially searched for a specified "minor name", or data object, to obtain a virtual storage copy of that data object. As data objects are placed into a virtual cache, existence information, implicit in the naming structure, is captured and saved. This information is relied on later in retrieving objects from the cache. The data isolation provided by maintaining class data and control blocks in individual data spaces is exploited to prevent failures relating to one class of objects from affecting the others, and to handle latent program users, following failures, effectively.An LRU-like trimming technique is used to remove less useful objects from the cache when cache space is fully utilized.

Abstract: A method for efficient generation of complied code is presented. In order to gain significant performance advantage with a minimum of code expansion, out-of-line code sequences are used. An out-of-line code sequence is a series of instructions that are invoked by a simplified calling mechanism in which almost no state-saving is required. Additionally, out-of-line code sequences is designed so that a single copy can exist on a system and all processes running on that system can access it. A series of out-of-line code sequences can be generated, each member of the series being tailored to a particular combination of compile-time information.

Abstract: A computer system includes a processing unit and an external storage holding a virtual data set including an address translation table in addition to data and program. The processing unit includes a real storage for holding an address translation table transferred from the external storage when the virtual data set is opened and an address translation mechanism for making access to the real storage by translating the virtual address to the real address with the aid of the address translation table. When the data required by the processing unit is absent on the real storage, the processing unit transfers the virtual address to the external storage and holds the data transferred from the external storage on the real storage.

Abstract: A personal computer is disclosed having a high speed microprocessor which executes in a variety of selectable speed modes to provide greater compatibility with application programs written for slower speed microprocessors. A logic means is included responsive to a speed select signal which does not change the speed of the microprocessor oscillator (clock) but rather changes the length of a wait state or "STOP" state of the microprocessor. In the STOP state the microprocessor (CPU) does not run bus cycles until the timer times out thereby releasing the CPU STOP. By varying the length of the time delay of the one-shot timer, the microprocessor simulates microprocessor speed changes which have the appearance of earlier generation computers with older microprocessors.

Abstract: A data processor which is so constructed that an operation code decoder decodes an operation code in an instruction to be processed comprising an operation code and an operand descriptor, and an addressing mode decoder decodes the operand descriptor, so that when the addressing mode of the operand is detected to be a specified addressing mode, for example, a register direct addressing mode, an entry address of microinstruction generated by the operation code decoder is modified, thereby enabling the entry address, different in microinstruction during the specified addressing mode and others, to be generated without increasing the number of product terms of a PLA in an instruction decoder.

Abstract: A technique for performing joins in parallel on a multiple processor database system effectively deals with data skew. The join operation is performed in three stages with an optional fourth stage. The first stage is a preparatory stage, the detail of which depends on the underlying join algorithm used. This preparatory stage provides pre-processing the results of which are used in the following stage as the basis for defining subtasks for the final join operation. The data provided in the first stage is used in the second stage to both define subtasks and to optimally allocate these subtasks to different processors in such a manner that the processors are close to equally loaded in the final join operation, even in the presence of data skew. This second stage is an assignment stage the details of which depend on the underlying join algorithm.

Abstract: A method and apparatus for performing storage and retrieval in an information storage system is disclosed which uses the hashing technique. In order to prevent contamination of the storage medium by automatically expiring records, a garbage collection technique is used which removes all expired records in the neighborhood of a probe into the data storge system. More particularly, each probe for insertion, retrieval or deletion of a record is an occasion to search the entire chain of records found for expired records and then removing them and closing the chain. This garbage collection automatically removes expired record contamination in the vicinity of the probe, thereby automatically decontaminating the storage space. Because no long term contamination can build up in the present system, it is useful for large data bases which are heavily used and which require the fast access provided by hashing.

Abstract: An interrupt processing method and an interrupt processing apparatus provides an end indicative information storing unit for storing an end indicative information of a daisy chain for at least one of a plurality peripheral units, the peripheral unit receiving the indicative information when the peripheral unit receives an acknowledge signal but does not output a request signal, and the peripheral unit outputs a specific chain end state signal to the central processing unit, so that the central processing unit is returned from a response waiting state. Therefore, when an error request signal is produced by noise, etc., delay at a central processing unit is reduced. Further, the daisy chain connection is cut at an optional portion and a request signal from an irrevelant peripheral unit is ignored, so that the efficiency of the processing is improved.

Abstract: A method for allowing a system administrator, application programmer, and/or program user to adjust the processor assignment function in a multiprocessor system. The system administrator controls the assignment function by defining certain system variables and flags. The application programmer can adjust the assignment function by causing allocation parameters to be passed in a system call before execution of the assignment function. To adjust the assignment function, the program user executes a system command that inserts similar allocation parameters into the program object code file stored in a file system on the multiprocessor system. The program executing the assignment function is responsive to the system variables and flags as well as the allocation parameters and performs the assignment function as it has been adjusted on a system, program or user level basis.

Abstract: The microcomputer has a plurality of register banks, each having a plurality of registers for containing data therein, a bank address register for holding the address of one of the register banks to be accessed and an access control circuit responsive to a bank address signal for putting one of said register banks in accessible condition. Part of the instruction code is utilized to modify the output of the bank address register during a portion of the execution cycle to permit single instruction transfer or arithmetic operations between plural memory banks.

Abstract: In a multiprocessor system (FIG. 1) wherein each adjunct processor has its own, non-shared, memory (22) the non-shared memory of each adjunct processor (11-12) comprises global memory (42) and local memory (41). All global memory of all adjunct processors is managed by a single process manager (30) of a system-wide host processor (10). Each processor's local memory is managed by its operating system kernel (31). Local memory comprises uncommitted memory (45) not allocated to any process and committed memory (46) allocated to processes. The process manager assigns processes to processors and satisfies their initial memory requirements through global memory allocations. Each kernel satisfies processes' dynamic memory allocation requests from uncommitted memory, and deallocates to uncommitted memory both memory that is dynamically requested to be deallocated and memory of terminating processes.

Abstract: In a distributed processing system having a least an originating node and a responding node connected through a communication path, the responding node comprising a plurality of processors and a memory device and where each of these processors is capable of accessing information from a corresponding database residing within the memory device, the inventive method involves: storing context information for an associated conversational transaction using a first processor situated within the responding node wherein the context information is stored at a pre-defined address in a first database residing within the memory device and associated with the first processor; producing a first message using the first processor for transmission from the responding node over the communication path to the originating node wherein the first message contains a first transaction identifier field having a value that corresponds to the pre-defined address; generating within the originating node a second message for transmission fr

Abstract: A control and arbitration unit for use in a remote terminal coupled to a system bus over which data encoded in military standard 1553B format is transmitted manages the flow of data between a local processor, a remote terminal interface coupled to the system bus and a local memory so that data transfers occur in an orderly fashion.

Abstract: A data processor with development support features includes an alternate mode of operation in which instructions are received by means of an externally-controlled path. The connections used by the externally-controlled path are not shared by any system resources accessible to the data processor in the normal mode of operation, but are used by other development support features in the normal mode. In a preferred embodiment, an integrated circuit microcomputer includes such a data processor as its CPU. The CPU has access to on-chip peripherals and memory, in addition to off-chip peripherals and memory, in both the normal and alternate modes of operation, by means of a parallel bus which it operates as a bus master. In the alternate mode, the CPU receives instructions by means of a serial bus on which the CPU is a slave device.

Abstract: A method for ensuring data integrity in a computer system having a primary logical device and one or more alternate logical devices. These logical devices have substantially identical data stored in them and have the capability of responding to requests. The system duplicates device access to the alternate logical devices. The logical devices are identified to the computer system as the devices on which duplicating or mirroring operations are to be performed. A read operation or a write operation is performed on the primary logical device. In the case of a write operation, it is also performed simultaneously on the alternate logical devices. The system waits for a response from the primary logical device. If the response indicates that the primary logical device has failed, the alternate logical devices are relied on to complete the operation.

Abstract: The present invention relates to methods of automatically generating a data stream in which a calendar owner can request the status of a plurality of calenders maintained by an electronic calendaring system. A first data structure is generated by the system in response to the entry of calendar information by the calendar owner. The first data structure includes a plurality of predetermined fields for storing the calendar information. Each of the plurality of fields are compared to equivalent fields in identified ones of the plurality of calendars. A second data structure is then generated for each of the identified ones of the plurality of calendars which sets forth the status of calendaring an event thereon. The second data structure is transmitted to the calendar owner to confirm the status of each of the identified ones of the plurality of calendars.