Abstract: A data transfer system having a transfer discrimination circuit for discriminating the type of data transfer between an input/output channel device and I/O devices for a computer includes a transfer discrimination circuit. This circuit includes a edge detection unit operating in response to a tag signal supplied to the edge detection unit for detecting the trailing edge of the tag signal after a leading edge of the tag signal has passed. The edge detection unit having a leading edge detector, a trailing edge detector, a storage element, and logic gate circuits. A timing unit is included operating in response to the output of the edge detection unit for counting a predetermined time, along with a discrimination storage unit operating in response to the output of the timing unit for delivering an output indicating an interlock data transfer or an output indicating a data streaming feature data transfer.

Abstract: A controller for transferring data between a plurality of data storage and retrieval devices and a plurality of computer workstations, and which is especially applicable to transferring bit-mapped image data. The controller responds to requests from a plurality of ports on the controller, connected to computers or similar devices, for connection to selected ones of a plurality of channels connected to the data retrieval devices. The connect request is decoded by the controller, and if the requested channel is available, the controller will interconnect the two devices. The controller allows simultaneous access by any of the ports to any of the channels not being used by another port. The device is in modular form so that a single design can be configured to efficiently operate in different applications. The controller is cascadable to allow larger numbers of devices to be connected.

Abstract: An input or input-output management circuit for a process control system such as a programmable automation is provided, including a serializing means with parallel inputs connected to input channels by filtering and threshold means, a series output of the serializing means being connected via a series connection equipped with an optocoupler and a filter to an input or input-output management unit.

Abstract: Visual and/or audible user prompts are adaptively provided to different users of a public video phone terminal (or other data or communication terminal) on the basis of user data which is determined during a predetermined sequence of user actions and compared with stored reference data. The time from the output of a prompt to the execution of an action by the user is measured, and the number of user errors per prompt is determined. The data thus obtained is compared with reference data characteristic of an average user. A user rated as unpracticed (i.e., below average) is then given more detailed prompts than an average user, and a user rated as practiced (i.e., above average) is given fewer or no prompts.

Abstract: A data processing system includes a planar board having a central processing unit (CPU), a main memory unit, and input/output (I/O) sockets or slots, each adapted to receive a selected one of a plurality of different and/or similar option cards. each card contains (or is connected to) and controls a respective peripheral device; and each card is pre-wired with an ID value corresponding to its card type. Software programmable option registers on each card store parameters such as designated default (or alternate) address information, priority levels, and other system resource parameters. A setup routine, during initial power-on, retrieves and stores the appropriate parameters in the I/O cards and also in slot positions in main memory, one position being assigned to each slot on the board. Each slot position is adapted to hold the parameters associated with the card inserted in its respective slot and the card ID value.

Abstract: A controller integrated circuit, such as a cathode ray tube controller, constituting a part of a microcomputer system comprises a plurality of internal registers, a designating register to which data designating at least one of the internal registers is set, a selection circuit selecting one of the internal registers by the data of the designating register, a first external terminal to which the data of the register selected by the selection circuit is supplied, and a second external terminal to which a timing signal representing the timing of the data supplied to the first external terminal is supplied. According to this circuit construction, the data inside the controller integrated circuit can be easily referred to be the control of the first register and by use of the first and second external terminals.

Abstract: A multiprocessor system includes a system of store queues and write buffers in a hierarchical first level and second level memory system including a first level store queue for storing instructions and/or data from a processor of the multiprocessor system prior to storage in a first level of cache, a second level store queue for storing the instructions and/or data from the first level store queue and a plurality of write buffers for storing the instructions and/or data from the second level store queue prior to storage in a second level of cache. The multiprocessor system includes hierarchical levels of caches, including a first level of cache associated with each processor, a single shared second level of cache shared by all the processors, and a third level of main memory connected to the shared second level cache. A first level store queue, associated with each processor, receives the data and/or instructions from its processor and stores the data and/or instructions in the first level of cache.

Abstract: A memory system that includes several memory locations connected to a reading circuit that provides read access to the memory location. The memory system also includes the controller that receives control information. A writing circuit is further included that provides write access to either only a first portion of the memory locations, or simultaneously several portions of the memory locations is designated by the control information. This invention further includes a memory system that provides several memory locations for the storage of information together with the controller having a first port and a second port. The first port provides access to the memory locations in response to a first address range and the second port provides access to the memory locations in response to several address ranges wherein at least one of the address ranges of the second port is different then the address range of the first port.

Abstract: Data communication through a composite network constituted by a plurality of mutually connected individual networks. When a center connected to a first network such as a wide-area telephone network and DDX for collecting information such as maintenance/management information performs data communication with a plurality of work stations connected to a network such as LAN, the information collecting center transmits a composite command containing collectively assembled addresses of the object work stations and operation commands to these stations. The composite command is disassembled in the second network. According to one method, the command is executed by the relevant work station upon reception of the composite command which is subsequently transferred to the succeeding station.

Abstract: Data messages are transmitted between host data processors and a communications processor. Data messages from a communications processor are transformed for the host processor to which the message is assigned. Data messages from a host processor are transformed for the communications processor. Protocol is established between (a) untransformed data messages from the communications processor and transformed data messages for the communications processor, and (b) untransformed data messages from each host processor and transformed data messages for each host processor. A device interface connects a plurality of host processors to a plurality of buses, each bus being connected to one communications processor. The device interface handles the protocol, transformation and control function in parallel so that messages between a given host processor and terminal connected to a communications processor are processed through a device interface.

Abstract: An extended addressing system for allowing use of existing circuit boards but obtaining more address space is disclosed. If given bits in the address value indicate that a former system board address is being presented previously unutilized higher order bits are used as a slot identifier that slot's AEN signal is made low, while all the remaining AEN signals to each slot are made high to disable operation. All the AEN lines remain low as an existing circuit board address is presented or a memory operation is occurring. All the AEN lines go high during a DMA operation.

Abstract: A method and apparatus for performing storage and retrieval in an information storage system is disclosed which uses the hashing technique. In order to prevent contamination of the storage medium by deleted records, a hybrid hashing technique is used which uses a fast, contaminating deletion of records during times of heavy load on the system, but uses a slow, non-contaminating deletion when the load on the system is not as heavy. The slow, non-contaminating deletion automatically removes previously generated contamination in the vicinity of the slow, non-contaminating deletion, thereby automatically decontaminating the storage space. Because no long term contamination can build up in the present system, it is useful for large data bases which are heavily used and which require the fast access provided by hashing.

Abstract: A data transmission apparatus which is connected with a shift register of a plural stages forming a forward path of data transmission line, and a shift register of a plural stages forming a backward path of the same, and a loop-back part therebetween, and comprises bypasses between the shift register on the forward path and on the backward path to bypass the transmitted data when significant data does not exist on the loop-back part side from a stage on which the bypass is comprised and no data stays at a stage where the bypass is comprised, so that data is transmitted at high speed, and which is constructed to be able to control the bypass from external, so that testing of circuitry is easy.

Abstract: In a computer system, a board voltage reading circuit or a board voltage setting circuit is formed on a board, to effectively read and set the power voltage of the board carrying various types of circuit elements. Board identification number data and board voltage reading mode data are entered into the board voltage reading circuit, and the board voltage setting data is entered into the board voltage setting circuit. These data are entered through a support processor by a display in a console. Only when the board identification number input from support processor and board identification number preset are in agreement each other, the board voltage is read by the board voltage readig circuit. The result is displayed by the display. The board voltage setting circuit is used for setting the power voltage of the board.

Abstract: The present invention relates to a technique for interfacing a plurality of remote terminals, as, for example, Craft Access Terminals (CATs), directly to a central database in a system, such as, for example, a Craft Access System, without interfacing with an intermediate center such as, for example, a centralized Repair Service Bureau and its personnel. An Applications Processor Microcomputer (APM) module includes a General Data Transport (GDT) to provide a powerful microprocessing environment and multiple data communication interfaces, and an Applications Interface Module (AIM) to provide the appropriate signal interface with the database system, the GDT, and the remote terminals.

Abstract: A bus arbiter for a multi-processor computer provides fair access by dynamically adjusting a base variable of a counter which is determined from a processor number of a previously access-requesting processor having the highest processor number. The counter then varies priority between a minimum processor number, such as zero, and the base variable of the counter. The priority signal from the counter and the current access-requesting processors are then provided to a memory device. The memory device is used to determine which current access-requesting processor is permitted to access the bus.

Abstract: In a method for monitoring and collecting data in a multi-tier computer system, a database operation message, referred to as an "open" message is transmitted to a database cache computer with a list of data items in the database cache computer to be monitored on a change-of-state basis. The database cache computer responds by monitoring the data items and returning unsolicited "change data" messages containing only states for data items which have changed over the monitoring period. The change data messages are sent back periodically without the need for polling by a higher-level computer. The monitoring process is terminated by closing data records in the higher-level computer which generates a "close" message to the database computer to terminate the transmission of the change data messages. Also disclosed is a database cache computer and a user interface computer for carrying out the method.

Abstract: Microprocessor architecture for an address translation unit which provides two levels of cache memory management is described. Segmentation registers and an associated segmentation table in main memory provide a first level of memory management which includes attribute bits used for protection, priority, etc. A second page cache memory and an associated page directory and page table in main memory provide a second level of management with independent protection on a page level.

Abstract: A programmable integrated circuit logic array device having one or more of the following features: (1) a bus port for receiving data directly from or making data available directly to an associated microprocessor or other similar device, (2) an internal bus (preferably with internal bus arbitration logic for resolving competing demands for utilization of the bus) for conveying data between the bus port and the logic arrays and/or between the logic arrays themselves, (3) the ability to operate either in an edge-trigger mode (in which controlled functions such as input registers are triggered by the transitional edges of control signals) or in a flow-through mode (in which controlled functions such as input registers are triggered by the states rather than the transitional edges of the control signals), and (4) the ability to operate either in a fast mode (in which timing control signals are applied substantially directly to the elements to be controlled) or in a slow mode (in which timing control signals propa

Abstract: High availability is achieved in a multiprocessor system by grouping the processors into two clusters operating on different clock and power boundaries. In each cluster is an array containing a substantially identical copy of the system information relating to the operation of the processors. Each processor has a local port for accessing the local array and a remote port for accessing the remote array. When an update is made on the system information, it is made on both the local and remote arrays with the remote update performed transparently.