Abstract: A terminal communications circuit that provides communication through a bus interface circuit to a network bus in accordance with the predetermined communications procedure, the terminal communications circuit including a communications interchange circuit that exchanges protocol signals with the bus interface circuit in response to commands received from a signal state controller that is resident in the terminal. The communications interchange circuit further provides communications state change information to the signal state controller to indicate the contents of the protocol signals from the bus information circuit. The signal state controller executes one of a plurality of program states to control communications over the network bus in accordance with predetermined communications procedure by providing commands to the communications interchange circuit in acordance with the program state that the signal state controller is currently executing.

Abstract: A cache memory includes an address modification circuit for operation during a cache block fetch sequence. The address modification circuit is connected to a polling circuit which receives a first word address from other portions of the cache memory connected to an instruction unit. The polling circuit tests whether a memory module storing the first word is free to make a data return transfer to the cache memory. When the memory module indicates that it is inhibited from making the data return to the cache memory, the address modification circuit selects in order of priority the next word in a cache block to be fetched and polls a memory module storing the next word. Word address selection and polling continues until a free memory module responds or until all words in the cache block have been fetched from main memory.

Abstract: A design methodology for digit serial architecture, especially for use in digital signal processing circuitry, includes a cell stack configuration incorporating a variable number of individual operation cells in conjunction with cap and control cells to provide power, control and timing signals. The arrangement employed permits the construction of cell libraries for silicon compilers from a small number of individual components and permits such compilers to generate chip fabrication masks for a plurality of fixed, but initially arbitrary digit size circuit designs.

Abstract: A method for forming a file of messages for a computer program including the steps of first forming a first file portion as a message word table having entries corresponding to the message words, said entries ordered in the table by their frequency of occurrence in the messages. Then forming a second portion as a message token string table containing a token string for each message where each token string includes several tokens, each representing a word or variable in the message. The tokens are located in the string according to the location of the corresponding words in the message. Each token has a value that represents the location of its corresponding word in the message word table. The third step includes forming a third file portion as a message look-up table that contains a unique identifier for each message and a corresponding pointer that indicates the address of a token in the token string table.

Abstract: An artificial neural system employs digital elements that may be fabricated using state of the art technology. The system includes a plurality of digital neural processors, each of the processors containing at least one register for storing a number; a signal is applied to the register to selectively increment or decrement the number stored in the register; circuitry is provided for resetting the register and for processing the number stored in the register. The neural system is trained by incrementing and/or decrementing numbers stored in the registers.

Abstract: An apparatus provides for recovery from a loss of synchronization in a queued data transfer between a controller and a peripheral device. The apparatus eliminates the need for a timeout mechanism within the controller. A method of operating the apparatus provides proper sequencing following a loss of synchronization as well as the correct status report for the data transfer which immediately preceded the loss of synchronization.

Abstract: Circuit and method is disclosed which prevents contention on a pulse-code modulated (PCM) bus, when different drivers are transmitting during adjacent time slots. The driver circuit switches automatically from a strong driver to a weak driver depending on whether a signal level is merely repeating or whether the level is transiting. Also the driver always employs the strong driver at the onset of transmission.

Abstract: A plurality of n-dimensional modular entities are internally interconnected via as many as n duel port random access memory devices (DPRs), each memory device dedicated solely to the interchange of information between two modular entities in an n-dimensional lattice of modular entities. One or more of the modular entities may itself be a separate multiprocessor architecture.

Abstract: The invention is a Clock for synchronizing operations within a high-speed, distributed data processing network. The clock is actually a distributed system comprising a Central Clock and multiple Site Clock Interface Units (SCIU's) which are connected by means of a fiber optic star network and which operate under control of separate clock software. The presently preferred embodiment is as a part of the flight simulation system now in current use at the National Aeronautics and Space Administration (NASA) Langley Research Center (LaRC), Hampton, Va.

Abstract: A memory control interface is provided for use with at least one external memory device used in conjunction with a microprocessor based system of the type providing address, control and data signals and having a basic input/output operating system for providing predefined instructions. The memory control interface apparatus receives the address, control and data signals from the microprocessor based system. Decoder circuitry decodes the received signals to identify predetermined signals corresponding to the predefined instructions. Timing circuitry responsive to the identified predetermined signals produces timing signals. Enabling circuitry responsive to both the identified predetermined signals and the timing signals generates an enable signal for coupling the microprocessor based system and the external memory; only after reliable operation of the microprocessor based system is identified.

Abstract: An information processing unit comprises an external input for acquiring the intention of a user as external process specifying information and data to be processed as source information; downward input for acquiring the intention of the user as inter-unit process specifying information via another unit of the same constitution as an upper unit for sending the inter-unit process specifying information; an upward input for acquiring the results of the processing outside of the unit as input of inter-unit processed information via at least one unit of the same constitution as a lower unit for sending the inter-unit processed information; processing device for re-composing the external process specifying information and/or the inter-unit process specifying information into process specifying information for own unit and inter-unit process specifying information for the lower unit and for executing the processing utilizing the source information and/or the inter-unit processed information according to the process

Abstract: When a microprocessor fetches an instruction to be processed by a coprocessor, it sends to the coprocessor a command corresponding to the instruction while informing the coprocessor that the bus cycle is in the mode of transfer of the instruction to the coprocessor. In transferring an operand from the memory to the coprocessor, the microprocessor asserts, in addition to a usual memory read signal, a signal (CYCYCL) indicative of validity of the coprocessor and instructs the coprocessor to fetch data to thereby complete the operand transfer from memory to coprocessor within one bus cycle. In transferring data from the coprocessor to the memory, the microprocessor asserts, in addition to a usual memory write signal, the CYCYCL signal and instructs the coprocessor to deliver the data to thereby complete the data transfer from memory to coprocessor within one bus cycle.

Abstract: A paged memory management unit (PMMU) adapted to translate each of a plurality of logical addresses into a corresponding physical address using a selected one of a plurality of descriptors comprising one or more translation tables stored in a memory, the PMMU assembling each of the logical addresses and the corresponding physical address into a respective translator.

Abstract: The vector processing apparatus fetches vector operands designated by an instruction from a storage to an operand buffer in a vector processor. The vector processor reads out and processes the elements of the vector operands stored in the operand buffer. The vector processor controls fetching of the element to be next processed from the operand buffer in accordance with the operation result. Thus, a vector operation of a type in which the increment of the indices of the vector operands depends on the operation result is carried out.

Abstract: A method and apparatus for marking data that is temporarily cacheable to facilitate the efficient management of said data. A bit in the segment and/or page descriptor of the data called the marked data bit (MDB) is generated by the compiler and included in a request for data from memory by the processor in the form of a memory address and will be stored in the cache directory at a location related to the particular line of data involved. The bit is passed to the cache together with the associated real address after address translation (in the case of a real cache). when the cache controls load the address of the data in the directory it is also stored the marked data bit (MDB) in the directory with the address. When the cacheability of the temporarily cacheable data changes from cacheable to non-cacheable, a single instruction is issued to cause the cache to invalidate all marked data.

Abstract: A communications base microcontroller particularly adapted for use with a multiplexing character processor of the type that multiplexes data characters to and from a plurality of communication lines to a central processing unit. The communications base microcontroller is operable with communication lines carrying various protocols and data rates. A scan list and direction control stores the order in which the communication lines are to be scanned and the direction of the next data flow. An instruction execution unit in response to the scanning order set by the scan list fetches instruction words during a machine cycle preceding an execution cycle and provides operands and instructions each associated with the particular communication line being scanned. A program control device, in response to multiplexing rate (scan rate) established by the scan list stores the present instruction, the input protocol and other functions and selects a pointer to the next program instruction.

Abstract: A parallel data processor is disclosed, in which a plurality of fundamental computing elements each comprising a computer and a memory are connected in a two-dimensional lattice configuration, each of said fundamental computing elements being operated by an identical instruction provided by a single control section, and in which said each fundamental computing element is provided with a shift register having ability of data transmission to the memory in said element and of further data transmission, which is asynchronous to operation in said element, between the adjacent fundamental computing elements, said latter data transmission being conducted concurrently to the operation in said element.

Abstract: An object-oriented, distributed data base system separates into a plurality of virtual partitions following communication failure between sites accessing the data base. Each partition accesses a separate copy of an initial data base and independently updates groups of data objects included in the data base to add new versions of data objects to the data base. Each virtual partition maintains a copy of all previous versions of data objects and maintains a change list describing all group updates that it executes. Following restoration of communication between sites, each virtual partition merges the data bases maintained by separate partitions to form a consistent merged data base permitting versions of data objects and collections of data objects created by any one of the separate virtual partitions to be identified and accessed in the merged data base.

Abstract: Bypassing of data from a main storage unit to an instruction and operand processing unit around an intermediate storage unit improves performance in a data processing system. The instruction and operand processing unit supplies requests for operands to the intermediate storage unit or cache. If the line is missing from the cache, the request operand is retrieved from the main storage unit. A bypass data path is connected between the main storage unit, prior to error detecting means in the cache, and the instruction and operand processing unit for transferring requested operands to the instruction and operand processing unit directly. Control, coupled to receive requests for operands and to the instruction and operand processing unit, signals the instruction and operand processing unit to receive the requested operands from the bypass data path when the data includes a requested operand.

Abstract: In a method of controlling the operation of a security module, wherein firmware controlling the operation of the security module (10) is stored in a program memory (40), new firmware may be loaded into the module (10). An authentication key (KA) is encrypted using a key storage key (KSK) stored in a resettable shift register (54) in the security module and the encrypted authentication key is stored in a secure memory (36). A firmware authentication value FAV is calculated, using the authentication key (KA), externally of the security module (10), for the new firmware, and the new firmware, together with FAV is loaded into a data memory (38) in the security module (10). A processor (30) in the security module (10) recalculates the firmware authentication value using the stored authentication key (KA) and compares the recalculated value with the loaded value FAV. If a correct comparison is achieved, the new firmware is transferred into the program memory (40).