Abstract: An address translation circuit for translating a logical address into a physical address in a computer system using a virtual storage method includes two high-speed buffers (TLB's) for an instruction and an operand, respectively. One of the buffers is selected for use at the time of a memory access depending on a signal supplied from a processing unit to indicate whether the memory access is related to an instruction cycle or an operant cycle. This configuration enables a high-speed address translation without lowering the TLB hit rate and without increasing the amount of the hardware components.

Abstract: A method of compactly storing digital data includes the steps of sequentially entering a plurality of digital data entries into a shift register having a plurality of stages and summing successive groups of data entries as they are outputted from the shift register to produce singly compressed data entries that are subsequently entered into a second shift register. Sets of singly compressed data entries which are outputted from the second shift register are again added to obtain doubly compressed data entries which are entered into a third shift register. This process continues until a sufficient number of shift registers have been employed to accommodate all of the expected data entries.

Abstract: A peripheral DMA (direct memory access) system having a computer with an internal DMA controller and only one channel available for external DMA operations includes: a peripheral DMA controller coupled between the computer address bus and a peripheral address bus, and also between the computer data bus and a peripheral data bus. The peripheral DMA controller includes a dual port "frame map memory" in which addresses of various peripheral devices are sequentially stored prior to initiating a DMA operation wherein data is rapidly transferred from various peripheral devices having nonsequential addresses to sequential locations of the computer memory or vice versa.

Abstract: The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest programming systems in the different partitions of the system. The main storage, expanded storage, the channel, and subchannel resources of a system are assigned to the different logical partitions in the system to enable a plurality of preferred guest programming systems to run simultaneously in the different partitions. This invention automatically relocates the absolute addresses of the I/O channel and subchannel resources in the system to their assigned partitions. Also the absolute and virtual addresses of the different guest programming systems are relocated into, as well as page addresses for any expanded storage, their assigned partitions.

Abstract: A method and apparatus for accessing data in a data base that provides for a minimum of unused storage while preserving easy expandability. A group of accessing keys are used to identify the attributes data that is being sought in a data base. In accordance with the invention, subkeys are extracted from members of the group of data accessing keys and these subkeys are advantageously rearranged to form derived accessing keys. Subkeys are densely populataed if most values of a subkey are used in most systems. One of the derived accessing keys, derived from densely populated subkeys is used for accessing the tables of data attributes that are therefore advantageously densely populated. Another derived accessing key, derived from sparsely populated subkeys, is used for accessing a sparsely populated head table. Derived keys of intermediate population density are used for accessing tables intermediate between the head tables and the tables of data attributes.

Abstract: The present application invention relates to a method for restarting execution of an instruction interrupted due to a page fault. When a page fault occurs during an execution of an instruction, the pertinent page is loaded from an external storage into the main memory and then the access which has caused the page fault is executed again. After N steps of the microprogram that has executed the page fault access, the page fault exception processing is initiated and at the save/restore operation of the content of the microprogram counter, the content of the microprogram is decremented by N, thereby restarting the execution of the instruction beginning from the step of the microprogram which has achieved the page fault access.

Abstract: A computer system having a central machine, work stations and a background memory, wherein the central machine has an active state, a standby state, a battery power supply state and a rest state, a heart memory maintains the actual time and contains information indicating at what time of what days the active state should prevail. When the mains power supply fails the central machine goes over to the battery power supply state. When the latter is failing, the battery indicator is set in an "error" state. When the mains power supply reappears, it is inspected whether then the active state has to be maintained and under the control of an "error" position an initial program load operation is carried out. If admissible the central machine goes over to the standby state.

Abstract: A cache memory subsystem has multilevel directory memory and buffer memory pipeline stages shared by at least a pair of independently operated central processing units and a first in first out (FIFO) device which connects to a system bus of a tightly coupled data processing system. The cache subsystem includes a number of programmable control circuits which are connected to receive signals representative of the type of operations performable by the cache subsystem. These signals are logically combined for generating an output signal indicating whether or not the contents of the directiory memory should be flushed when any one of a number of types of address or system faults has been detected in order to maintain cache coherency.

Abstract: A cell controlling computer is interfaced to a group of station-level computers through an access machine which stores a database of data that is continually being updated from the station-level computers in response to conditions on machines and industrial process equipment. The access machine communicates with the station-level computers using messages addressed to each respective station. The access machine communicates with the cell controlling computer through database operations messages that allow data to be communicated for many stations at once. During on-line reconfiguration, new data items in the station-level computers can be added to the database in the access machine using other database operations messages.

Abstract: A peripheral control circuit for a computer system. Independent control and interface circuits are provided for left and right audio channels, for a communications port, for storage media, and for joysticks or paddles. Control logic is provided for direct memory access to system memory and for interrupts to the processor by each of the peripherals. Sound data corresponding to a sound waveform during a particular time period is fetched using DMA or interrupts. Registers store data for selecting the output rate of the sound data, the length of the sound waveform, and the volume of the sound waveform. Four audio channels and two separate audio ports are provide.

Abstract: A serial data direct memory access system including a control circuit that shares control with a master computer of an interface bus of a DMA storage system. Serial data is supply to the control circuit via a fiber optic cable. The control circuit employs means responsive to status code bits of the message words for gaining control from the master computer of the interface bus and for directly accessing the computer controlled bus memory storage system. This system is capable of handling data streams of infinite lengths. Also, means are provided for preventing bit errors from interfering with critical message words.

Abstract: A user selectable switch arrangement in combination with logic circuitry allows the timing of a central processor unit (CPU) to be switched between two clock frequencies. Operation at a higher frequency permits the CPU to perform an increased number of tasks per unit time and thus increases data throughput, while a lower operating frequency provides enhanced CPU hardware and software interfacing compatibility.

Abstract: In a semiconductor integrated circuit, an internal logic circuit outputs information for an external bus via buffer circuits. The output of the buffer circuit is placed in a high impedance state by responding to a control signal, and the information which is output from the internal logic circuit to the buffer circuits is held in the bus cycle during which the control signal is input. In the response to a release of the control signal by the input of the control signal, the interrupted bus cycle is released, and the information stored is output via the buffer circuit to the external bus.

Abstract: A computer system and method for data base indexing and information retrieval. A number of keywords are selected and each record of a data base is searched to determine in which records each keyword appears. The central processing unit of the system then creates a vector for each keyword which identifies each record number of the data base where the keyword appears and numerically sorts the record numbers. A special bit processor next transforms each vector into a bit string that is identified by one of the keywords. The bit strings are returned to the central processing unit and are stored in secondary storage so as to form an index for the data base. To retrieve information, one or more keywords are input to the central processing unit. The input keywords are used by the central processing unit to identify the bit string for each keyword. The keywords may be logically joined using "AND," "OR" and/or "NOT" commands.

Abstract: In response to the execution of a single loading instruction, the front half and the rear half of a designated vector may be stored in respective vector registers in a single processor operation. For this purpose, a data distribution circuit is interposed between a group of vector registers and a vector data storage for feeding the vector data read out from the storage to a first vector processor designated by an instruction without shifting and for shifting the respective components of the read-out vector data and feeding the shifted components to a second vector register designated by the instruction.

Abstract: A method for dynamically assigning and removing task affinity for a resource is disclosed and claimed. A first interrupt handler recognizes a special task interrupt condition which is generated by the hardware. The interrupt condition is generated because a task attempted to execute a special instruction and either a special resource is attached to the central processing unit which issued the special instruction, or a special resource is not attached to the issuing central processing unit, but could be attached to another central processing unit in a central electronic complex. The first interrupt handler then passes control to a second interrupt handler which determines if execution of the current task can continue. If it can, the second interrupt handler creates or reestablishes a special environment and the task is dispatched (either for the first time or again) with a special dynamic affinity to only those central processing units in the central electronic complex that have a special resource attached.

Abstract: A procedure for use in an optimizing compiler termed "reassociation" determines the preferred order of combining terms in a sum so as to produce loop invariant subcomputations, or to promote common subexpressions among several essential computations, by applying the associative law of addition. To achieve this, the requisite optimization of an object program or program segment, the following discrete steps must be performed after the strongly connected regions, USE and DEF chains have all been identified:1. Find the region constants and induction variables;2. Identify all of the essential computations;3. Write every essential computation as a sum of products;4. Exploit the use and DEF functions to substitute the definition of each operand R in an essential computation, if there is a unique computation of R in the strongly connected region and the defining operation is +, -, .times., or copy;5. Fix displacements;6.

Abstract: A register-stack apparatus comprising first and second registers, first and second stack memories respectively coupled to store the register contents, first and second modifiers for providing the respective register contents in predetermined modified forms, and first and second select means for receiving a plurality of inputs including the modified register contents and, in accordance with a control command, applying a single output to the respective registers for storage therein, is disclosed. The register-stack apparatus is implemented in the controller of a computing system in which the controller receives macro-instructions from a host computer and, in response, provides microcode to an attached computing device. The register-stack apparatus is implemented as a program counter, I/O device, and plurality of register files and enables execution of CALLs, INTERRUPTs, and RETURNs with a minimal number of no-op instructions being issued to the attached computing device.

Abstract: A circuit for protecting the contents of memory devices, each having a power supply voltage input terminal and a disabling signal input terminal following a failure in an A.C.-derived D.C. potential in which respective time delay circuits couple battery potential to said power supply voltage terminals and to said disabling signal input terminals at respective predetermined times after said failure.

Abstract: The present invention describes a resynthesized DRFM and method thereof. A conventional DRFM is utilized with the addition of a computer device. Once the digital pattern signals are stored they are utilized to generate a digital pattern which fills the interpulse period between the pair of signals. The interpulse digital pattern is then adjusted so that the digital pattern phases of the first and second signals match. In general the interpulse period digital pattern is not a uniform replication of the pulsed signal digital pattern because the adjustments have been made in order to accomplish pattern phase between the two pulses. These are then stored in memory until recalled.