Abstract: A method for converting an integrated circuit design to a phase-shift complaint mask design. The method comprises the steps of locating features of the integrated circuit that violate predetermined design criteria converting error flags to physical marker shapes, modifying the located features using layout modification system technology based on a predetermined cost constraint, determining if all violations are corrected, and either changing the cost constraint to a higher cost constraint if violations still exist and repeating the process or terminating the conversion if all violations are corrected.

Abstract: Methods and apparatus for use with electronic circuit design tools to define and test multiple power and ground domains within an electronic circuit design. The present invention defines a power and ground specification associated with a CAD/CAE tools design database. To build the power and ground specification, first, power and ground domains are defined and the circuit design is partitioned into one or more groups of devices which correspond to the power and ground domains. Second, power and ground signals are associated with these defined groups of devices. Lastly, this information is stored within a power and ground specification integrated with the information within the design database to allow the CAD/CAE tools to test the multiple power and ground domains within the IC or circuit board design.

Abstract: The present invention relates to an inventory control method and architecture that maximizes revenues derived from the sale of a given inventory resource to a customer. More particularly, the present invention uses a continuous nested execution environment that allows a determination of a minimum acceptable price by continuously computing an optimal sale price based on current demand and supply and expected cancellations. The method described accesses a centrally located information repository and retrieves an inventory resource type and value allowing requests below the minimum acceptable price to be rejected, while requests above the minimum acceptable price can be accepted thus allowing the resource provider to maximize incoming revenues from the sale of its inventory of reservations.

Abstract: A method of adjusting drive currents on a semiconductor device having transistors of various densities is disclosed. Consistent with the invention, off-state currents and drive currents associated with non-dense transistors on a first semiconductor device formed by a fabrication process are determined. Off-state currents associated with dense transistors on the first semiconductor device are also determined. Using the determined off-state and drive currents associated with the non-dense transistors and the off-state currents associated with the dense transistors on the first semiconductor device, drive currents associated with the dense transistors on the first semiconductor device are estimated.

Abstract: To implement a method of laying out interconnections, which is capable of reducing a skew value of a predetermined signal and a delay in predetermined signal to the utmost, a region intended for a wiring layout employed in a CAD system is divided into a plurality of subregions and wiring regions dedicated to the predetermined signal in the respective subregions are set. The number of driver's stages in the respective subregions is set and the region is enlarged with the adjacent subregions identical in number of driver's stages as virtual subregions. Thus, the layout of wiring between the subregions is set.

Abstract: A first microprocessor having a PH1/PH2 pipeline structure is designed. The first microprocessor undergoes a design cycle including microarchitecture, design (e.g. logic design, circuit design, and layout work), verification, qualification, and volume manufacture. Subsequently, a second microprocessor is derived from the first microprocessor by replacing the PH1 and PH2 latches with edge triggered flip flops connected to a clock line which is operable at approximately twice the frequency of the clock signals used in the PH1/PH2 pipeline. A minimal design effort may be employed to produce the second microprocessor. The microarchitecture of the second microprocessor is quite similar to the microarchitecture of the first microprocessor. Still further, much of the design, verification, and qualification work performed for the first microprocessor may be reused for the second microprocessor.

Abstract: A master-slice for semi-custom-made integrated circuit devices includes standard cells arranged in rows and columns, and the standard cells are respectively associated with additional signal drivers; when logical inconsistency takes place between results of a back annotation and results of LSI tests due to time delay during propagation of signal lines, the additional signal drivers are selectively connected to the signal drivers of the standard cells so as to increase the current driving capability, thereby making the results of the LSI tests consistent with the results of the back annotation.

Abstract: Disclosed are various techniques for deploying multiple processing resources, operating in parallel, to compile electronic designs. The disclosed methods identify "compilation tasks" that can be performed in isolation from the remainder of a large "compilation project." When one of these stand alone compilation tasks is identified, it can be temporarily segregated and performed by one or more processors which are not working on other tasks. Simultaneously, the remainder of the project compiles under one or more other processors. One class of severable compilation projects includes those projects that contain multiple full compilation tasks, each of which involves compiling a single design from start to finish. Another class of divisible compilation projects includes those projects in which the logical hierarchy of an electronic design provides the boundaries between isolated compilation tasks.

Abstract: A system and method for displaying an electronic program schedule guide is provided. The system has areas for displaying program schedule information. In addition, the system also has areas that may be used for displaying movie listings. The system has enhanced recording capabilities, including extending recording time, automatically rescheduling recording, and the like. Finally, the system has features which simplify the setup and installation procedures.

Abstract: A method and system for constructing polygon layout. From a schematic, there is a data file describing a series-parallel transistor structure having a plurality of gate regions and a plurality of source/drain regions. A representation list is created (either by a computer user or by a computer analyzing a netlist). This representation list includes a plurality of region data for the plurality of gate regions and the plurality of source/drain regions. Polygon layout is built for the series-parallel transistor structure from this representation list.

Abstract: Pattern data that is an object of correction is divided into an area on which correction is made using correction values that have been obtained in advance for patterns and their respective layouts and an area on which correction is made on the basis of correction values calculated by a simulator. For example, simulation-based correction is made on a gate layer in a memory, while rule-based correction is made on a gate layer in the other area than the memory on the basis of rules for active gate width only. After being subjected to the correction, the areas are combined.

Abstract: A method and a system in which a computing system transparently accesses resources connected to the Internet. A memory of the computing system contains an operating system, a cache associated with the operating system, a shared library and an access server. The shared library is responsive to a system call for a file by determining whether a path name for the file is located under a personal name space in the memory and by issuing a request for retrieving the file from an Internet resource based on the path name located under the personal name space when the file is not stored in the cache and has a path name located under the personal name space An access server, in response to the request from the shared library, selects an appropriate access protocol for retrieving the file from the Internet resource and retrieves the file from the Internet resource. The shared library then issues the system call to the operating system when the access server retrieves the file.

Abstract: In accordance with the teachings of the present invention, an improved method and apparatus for automatically locating the coordinated starting points of a differential pair is provided. In one embodiment, a profile of obstacles is constructed, wherein the obstacles are proximately situated adjacent to a first and second endpoint of a differential pair. A pair of coordinated starting points are determined, corresponding to the first and second endpoints, using the constructed profile. The coordinated starting points are used for routing the differential pair of traces in a coordinated manner.

Abstract: Enhanced capability design-rule halos for use in Computer Aided Design (CAD) software programs are described. Such enhanced halos, created around a design feature at the design rule distance from that feature, have the following characteristics: beveled corners for closer placement of adjacent non-parallel and/or non-perpendicular design features, level-to-level design rule halos, following a bend or turn in a design feature, the design rule halo automatically adapts to bends or turns in the design feature and associated changes in the design feature following the bend, following a bend or turn in a design feature, the design feature and the design rule halo automatically snap back, as required, to avoid a design rule violation with respect to an adjacent design feature, and the design-rule halo is prevented from extending closer to an adjacent design feature than the design rule distance. These actions are performed real-time and interactively.

Abstract: Type partitioned dataflow analyses perform a dataflow analysis of a program by partitioning the dataflow analysis into phases using types to help reduce costs attendant to the dataflow analysis of the entire program. Each phase models only a subset of the relevant program quantities and may be analyzed separately. Type partitioned dataflow analyses extend quantity-based partitioning to non-separable dataflow analyses by determining analysis-time dependencies connoting potential run-time interactions between relevant program quantities and scheduling the dataflow analysis of each program quantity after the dataflow analysis of all other program quantities upon which it depends.

Abstract: In a placing design employing standard cell system, a series of steps of merging, improving arraying in one-dimensional array and division are fundamentally alternately repeated to obtain a two-dimensional array of a plurality of cells which have relations interconnections. In the automatic cell placing method, since division is always performed after merging, placing obtained in the previous step can be corrected resulting in placing design having small dispersion in wiring density distribution.

Abstract: A system and method for efficient implementation of a multi-port logic first-in, first-out ("FIFO") structure or particular utility in high clock speed integrated circuit ("IC") processor design which provides for reduced on-chip area requirements and fewer and less timing critical electrical interconnect paths. The advantageous reduction in IC area and enhanced performance disclosed herein is enabled through the rotation of the inputs and outputs of the FIFO; maintenance of decoded head and tail pointers, and folding the FIFO entry locations such that the entries are arranged in an interleaved fashion.

Abstract: In a parallel database system having an execution device on a front end side and a plurality of execution devices on a database operation side (hereinafter referred to as the "divided data side"), the front end side analyzes a definition statement of a routine such as a function or a procedure inputted from a user to create routine execution process instructions for executing the routine. Simultaneously, the front end side determines whether or not a database operation statement is contained in the routine, and creates check information indicative of the determination result. The front end side analyzes a query statement inputted from the user to create a first query execution process instruction to be executed on the front end side and a second query execution process instruction to be executed on the divided data side.

Abstract: A method enhances the presentation of search results from a structured database. In accordance with the method, a search query including two or more attribute/value pairs is presented to a system. The system then identifies a plurality of records which each minimally match the search query. Each document or record in the plurality of identified records is assigned a weight based on at least two factors: the extent to which the record matches the entire search query; and the relative frequency with which the attribute/value pair that matches the given record matches the records of the remainder of the structured database. The plurality of records that minimally match the search query are then identified to the requester in ranked order based on the assigned weights.

Abstract: A mask programmable IC is provided that includes dedicated boundary scan logic in the I/O cells. Valuable core logic resources therefore need not be consumed to implement boundary scan logic. In one embodiment, one boundary scan cell is provided per I/O cell. Another embodiment provides great flexibility in emulating any of several FPGAs in any of several packages. In this embodiment, two boundary scan cells are provided for each I/O pad, each cell alone being capable of providing the boundary scan functions associated with one I/O pad. By selectively choosing which of the boundary scan cells are included in the boundary scan data chain, the order of the boundary scan chain of the emulated FPGA in any of two or more packages can be reproduced. Boundary scan behavior is therefore emulated as well as the programmable logic behavior of the FPGA. In one embodiment, additional programmable interconnect lines traversing each boundary scan cell are provided.