Abstract: A device for reducing evaluation time of a matrix representing an electrical circuit. Conductance values of each circuit component in the circuit are written to corresponding models utilizing non-blocking writing techniques. The matrix is represented by a reduced memory structure where each matrix node is represented by a matrix element structure having at least one pointer to a conductance value contained in a model structure corresponding to a circuit component that contributes to a value of the matrix node. A set of rows or columns of the matrix are then processed to calculate final matrix node values independently.

Abstract: In a method of estimating wire length allowing highly precise estimation of the estimated wire length of a net, an object net is selected. Thereafter, the object net is developed into pin pairs. For each of the pin pairs, a subcircuit satisfying a prescribed relation with the pin pair is extracted from the semiconductor integrated circuit. From the subcircuit, information necessary for estimating wire length of the pin pair (number of nets in the subcircuit and total area of macro cells in the subcircuit) is extracted. Based on the extracted information of the subcircuit, estimated wire length of the pin pair is estimated. Based on the estimated wire length of the pin pair, estimated wire length of the object net is estimated.

Abstract: In a computer aided design system, a method of performing a layout process of an integrated circuit uses predetermined logic design and predetermined connection data. The connection data is changeable by an operator. The method includes the steps of generating new layout data using new connection data when the connection data is changed by the operator, replacing the layout data stored in the database with the new layout data, extracting parasitic elements from the new layout data to generate new parasitic element data; replacing the parasitic element data stored in the database with the new parasitic element data, computing signal delay times of the new parasitic elements to generate new delay time data; replacing the delay time data stored in the database with the new delay time data; and repeating above steps each time the connection data is changed by the operator.

Abstract: This invention relates to an advertisment machine which provides advertisements to a user searching for desired information within a data network. The machine receives, from the user, a search request including a search argument corresponding to the desired information and searches, based upon the received search argument, a first database having data network related information to generate search results. It also correlates the received search argument to a particular advertisement in a second database having advertisement related information. The search results together with the particular advertisement are provided by the machine to the user.

Abstract: Logic circuits are experimentally automatically synthesized, and a representative line length of each fanout number is estimated on the basis of a net list resulting from the synthesis. The representative line length corresponds to a length of a line positioned at a center when plural lines are aligned in the order of their lengths (namely, a median line length WLmed(fn)). Furthermore, a standard deviation .sigma.med(fn) and a probability coefficient K(fn) of the deviation are calculated with regard to each fanout number on the basis of the net list. Then, a defined line length WL(fn) of each fanout number fn is calculated by using an expression, WL(fn) =WLmed(fn)+K(fn).multidot..sigma.med(fn). At this point, when there is a demand for design of an LSI having a high operation speed, the probability coefficient K(fn) is set at a small value, and when there is a demand for design of an LSI completed in a short period of time, the probability coefficient K(fn) is set at a large value.

Abstract: A method for managing stepper operations required during the manufacturing of an integrated circuit die having at least one known defect, as determined by inspection, comprises the steps of determining, based upon an analysis of the connectivity and defect information relating to the die having at least one known defect a probability of failure to each at least one known defect and eliminating from stepper operations any die having at least one fatal defect.

Abstract: Many programming languages utilize reference pointers in computer code. Furthermore, some of these programming languages perform memory management in the form of garbage collection. Once such language is Java. During the execution of a garbage collection routine, the computer may need to locate all the variables containing reference values. The present invention introduces a method for run-time tracking of object references in computer code and determining which variables contain references to objects at garbage collection sites. The method of the present invention first creates a bit vector in memory. The bit vector is then initialized. Second, each variable declared in the computer program that may be used to store a reference value is assigned a unique bit within this bit vector. Each bit is maintained to indicate whether the variable it is assigned to is currently storing a reference value. Specifically, when a variable is assigned a reference value, the corresponding bit in the bit vector is set.

Abstract: A system for selectively recording a data structure where one or more external program modules are registered. A group of important actions is selected corresponding to both internal program modules and registered external program modules. The system determines if an action associated with one of the internal program modules or one of the registered external program modules has occurred. If so, the system determines if the action is one of the important actions. If the action is an important action, then information associated with the important action is placed into data fields of a data structure. The data structure containing the information is stored in computer memory. The data structure is maintained within a central container or folder in memory, along with previously recorded data structures. The data structure can be automatically deleted after a predetermined threshold of time.

Abstract: A method for programming complex programmable logic devices (CPLDs) to implement a logic function, whereby user-designated locked equations of the logic function are mapped into the macrocells of a function block, and then undesignated (non-locked) equations are mapped into the remaining macrocells. The method shifts product terms between the macrocells to adjust the placement arrangement of the mapped equations, thereby obtaining a placement arrangement which is both valid and meets user-defined timing constraints.

Abstract: A process (20) and design tool (62) are presented for the accurate prediction of design parameters (42) for components (38) of an integrated circuit (22) during the early stages of the design of that integrated circuit (22). These predicted design parameters (42) include pin count parameters (50), propagation delay parameters (52), layout area parameters (54), dynamic power parameters (56), static power parameters (58), and total power parameters (60). With these parameters, the designer interactively modifies the design prior to the layout and prototyping of the integrated circuit (22). The dynamic power parameters (56) and total power parameters (60) may be repetitively predicted with differing input items to establish a power usage pattern for the integrated circuit (22).

Abstract: A differential cascode voltage switch circuit includes a plurality of devices wherein a portion of the plurality of devices have a low threshold voltage and a remainder of the plurality devices have a regular threshold voltage for providing a performance gain without a substantial increase in standby power wherein at least one device has regular threshold voltage between a supply voltage and a ground. A method of producing a multi-threshold voltage circuit includes the steps of defining between a supply voltage node and ground at least one regular threshold voltage device for producing a high resistance to reduce current leakage and defining low threshold voltage devices within the circuit for reducing leakage current.

Abstract: A method and system for predicting the sensitivity of the integrated circuit logic cell timing performance to variations in voltage and temperature. Rather than using the prior art approach of multiplicative derating factors to model voltage and temperature effects on timing performance, adders are used to model the change in performance due to variations in operating conditions (i.e., voltage and temperature). The adders are treated as functions of input transition time (Tx) and output load capacitance (Cload). The change in performance as measured in time forms a plane over the Tx-Cload operating range for variations in either voltage or temperature. The adders, using a plane equation as a function of Tx and Cload, greatly improve the absolute accuracy in predicting the effects of variations in voltage and temperature, as compared to using the prior art methods involving multiplicative derating factors.

Abstract: A set of filters are arranged in sequence for verification and analysis of digital circuit designs. The filters are either active filters, which are directly involved in verification of circuit designs (e.g., a Binary Decision Diagram (BDD)-based verifier or an automatic test pattern generation (ATPG)-based verifier), or passive filters, which gather information about the circuit or transform the circuit structure in order to simplify the verification problem (e.g., random pattern simulation or circuit partitioning). Given a pair of circuits to be verified, the filter approach first subjects the circuits to very simple, fast techniques having very low memory usage requirements. These steps are followed by a series of increasingly powerful methods that are more time consuming and often require more computer memory for their operation.

Abstract: A circuit design method and a circuit design apparatus of this invention allow a judgement from a broader view based on high-level design information inputted upon a logic design to determine a rough packaging design. A rough placement position of a function block cell, which can configure a circuit that is an object of the design, unit on a circuit is determined on the basis of abstract circuit information in an abstract level higher than that of packaging design basic cell obtained in a logic design. On the basis of the rough placement position and the abstract circuit information, the function block cell is two-dimensionally developed into the packaging design basic cell, and a packaging design of the circuit that is an object of the design is performed. The method and apparatus of this invention is applicable to a design of a circuit such as an LSI, a PWB, etc.

Abstract: A integrated circuit (IC) chip with ESD protection level and the system and method of wiring the IC chip. Minimum wire width and maximum resistance constraints are applied to each of the chip's I/O ports. These constraints are propagated to the design and array pads are wired to I/O cells located on the chip. Thus, wiring is such that wires and vias to ESD protect devices are wide enough to provide adequate ESD protection level. The design is then verified by first identifying the chip pads, I/O cells and ESD protect devices. Connections between these three structures are verified. Wires between the ESD protect devices and the chip pads and I/O cells are shrunk such that unsuitable connections becomes opens (disconnected) and are found in subsequent checking. Finally connections to guard rings are checked. Power rails are checked in a similar manner.

Abstract: A post-placement residual overlap removal process for use with core-based programmable logic device programming methods that is called when an optimal placement solution includes one or more overlapping cores. Horizontal and vertical constraint graphs are utilized to mathematically define the two-dimensional positional relationship between the cores of the infeasible placement solution in two separate one-dimensional (i.e., horizontal and vertical) directions. Next, the constraint graphs are analyzed to determine whether they include a feasible solution (i.e., whether the overlaps existing in the placement solution can be removed simply by reallocating available resources to the overlapping cores). If one of the constraint graphs is not feasible, then the infeasible constraint graph is revised, and then the feasibility of both graphs is re-analyzed for feasibility. The feasibility analysis and constraint graph revision steps are repeated until both constraint graphs are feasible.

Abstract: An electronic checklist program is provided for commercially available printed circuit board layout design programs. The checklist program creates a file which is appended to a design file created by the layout program. The checklist program has step menus indicating steps for each interval to be completed in the layout design. When steps in an interval are completed, the time is logged for each and when an interval is done, the cumulative time is logged. The program tracks the last step completed such that on start-up with a previously created design, the program skips to the screen including the last completed step. Provision is also made to churn completed intervals and log churn time.

Abstract: An integrated structure layout of functional blocks and interconnections for an integrated execution unit of an integrated circuit chip. The functional blocks of the integrated execution unit include data dependency comparator logic, tag assignment logic, and register file port multiplexer logic. The data dependency logic receives address signals for a group of instructions and passes dependency information output to the tag assignment logic. The tag assignment logic provides tag information output to the register file port multiplexer logic. The tag assignment logic is arranged on opposite sides of a center channel, so that the tag information output is laid-out in the center channel and is fed directly to the register file port multiplexer logic in a substantially straight path. The register file port multiplexer logic directs the tag information output to a register file address port of a register file.

Abstract: A circuit is constructed on transistor level out of a net list and it is determined if the output node of a circuit for receiving a clock signal can go to a high impedance state from this circuit. If the output node can go to a high impedance state, it is designated as the starting point for a path searching operation and an input node of the circuit not receiving a clock signal is designated as the terminating point of the path searching operation. If, on the other hand, the output node cannot go to a high impedance state, the output node is designated as the clock node and an input node of the circuit not receiving a clock signal is designated as the terminating point of the path searching operation. With this arrangement, a sequential circuit can be divided into combinational circuits for certain.

Abstract: A technique for converting a software program into an object oriented class for sending across a network. A software program is loaded as instance data into a single object oriented class which is self-extracting. Preferably, each program file from the software program is compressed prior to being loaded as instance data into the class. The class may be a Java class which is sent over the Internet to a Java enabled computer system, where the class is unpackaged and the original software program recreated.