Abstract: A method is described herein for designing a circuit using graphic editor software. A graphic design file is generated corresponding to a block diagram created in a graphical user interface associated with the graphic editor software. The block diagram includes a plurality of blocks and a plurality of conduits interconnecting the blocks. A block design file is generated in one of a plurality of formats for each of selected ones of the plurality of blocks in the block diagram. Each of the block design files corresponds to an implementation of its corresponding block. Modifications to any of the graphic design file and the block design files are incorporated into each other under software control.

Abstract: When simulating a circuit's behavior, a transistor can be modeled to account for gate resistance induced propagation delay. In one embodiment, the model includes a transistor with a resistor connected to the gate of the transistor. The resistor has a resistance equal to one third of the gate resistance.

Abstract: A layout design method and system for a semiconductor integrated circuit improves circuit performances related to operated frequency and power consumption by improved placement and routing. The method features an intersecting wiring predicting step that predicts the number of the intersecting wirings based on predicted wiring routes and an intersecting wiring capacitance calculating step that calculates the capacitances between the intersecting wirings.

Abstract: A facilitation mechanism between users and databases is composed of a user agent for interfacing between users and the entire facilitation mechanism, a DB agent for interfacing between each database and the facilitation mechanism, and a facilitation agent for mediating between each of the agents, which are distributed. By adopting this system in the present invention, a facilitation mechanism in which scalability can be secured for an increase in the number of users, the addition of databases, etc., operation load and operation managing cost can be distributed, and security of information can be protected, can be realized.

Abstract: Managing a log stream of a computer system. An entry of a log stream, desired to be removed from the log stream, but not eligible for removal, is logically deleted. Logical deletion keeps the entry on the log stream and indicates that the entry can be removed from the log stream when it is eligible. When the entry is eligible, it is removed. If a desired entry remains at the tail of the log stream for a given period of time, thus not allowing the removal of one or more undesired entries, the desired entry is rewritten to the head of the log stream and deleted from the tail. Thereafter, other logically deleted entries eligible for deletion are removed from the log stream.

Abstract: Very high speed circuits are adversely effected by parasitic capacitances and line resistances. At high speeds these values of capacitance and resistance change with frequency. A method of verification of the design of high speed circuits includes a simulation of the effects of these changes in resistance and capacitance which occur at high frequency. There is a logic component and a physical-layout component which are combined to provide a full simulation of the circuit taking into account these effects which occur at very high frequency. The physical-layout component utilizes Maxwell's equations in their entirety without removing the time dependent effects. One embodiment considers only cases defined by the bus protocol, reducing the computational penalty of complete electromagnetic simulation.

Abstract: A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc.), properties of a particular scan chain (membership, name, etc.), test signals (scan-in, scan-out, scan-enable, etc.

Abstract: A method for improving the accuracy of quiescent current estimation for integrated circuits. When used with a CMOS process, the method involves selecting transistors having a polysilicon gate length corresponding to the minimum length permitted by process design rules. For each of the selected transistors, the intersection of the width of the polysilicon gate and the active area of the transistor is calculated. The widths of all of the selected minimum length devices are summed to generate a total width dimension value. The total width dimension value is multiplied by a predetermined quiescent current per unit width conversion value to produce an estimate of the quiescent current drawn by the integrated circuit. In an alternate embodiment of the invention, the total width dimension value is multiplied by a range of predetermined quiescent/leakage current per unit width values representing a range of testing conditions and temperatures.

Abstract: An in-system programmable and verifiable (ISPAV) configuration restoring device (CROP device) has an Electrically Erasable and reprogrammable, NonVolatile Integrated Storage array (e.g., a FLASH EE.sub.-- NVIS array) into which configuration instructions may be written for later readout during configuration restoration of a Programmable Logic Device (PLD) where the PLD has a volatile configuration memory. The volatile PLD may be an FPGA or a CPLD. The ISPAV CROP device includes a shared shift register through which configuration instructions read from the EE.sub.-- NVIS array are serially shifted out to a to-be-configured PLD. The shared shift register is also used for loading new configuration instructions into the EE.sub.-- NVIS array by way of a 4-wire interface such as JTAG and also for verifying proper writing of these instructions into the EE.sub.-- NVIS array.

Abstract: A data acquisition system for use with a computer includes an interface unit for interfacing with a computer; a control data memory for storing control data which is associated with controls for the computer; and a file data memory for storing file data which is to be acquired by the computer. A processing system is provided for controlling operation of the control data memory and file data memory, and for controlling transfer of data to the computer from the file data memory via the interface unit via a controllable data bus and an address/control bus.

Abstract: A method and apparatus is provided in which a site selection program is operable to selectively initiate sample testing of data transfer speed of a plurality of sites containing a predetermined data file. The methodology calculates a priority ordering of the plurality sites based upon the sample testing of data transfer speed, and divides the data file into portions for parallel access and delivery of the requested data file such that all of the portions are delivered to the user at approximately the same time, whereby faster channels will be requested to access and deliver larger file portions and relatively slower channels will be assigned to access and deliver relatively smaller portions of the requested data file. Upon receipt of the portions, the requested data file is assembled for further processing by the user.

Abstract: A graphical programming development system for creating a graphical program client, wherein the graphical program client is operable to programmatically access or invoke functionality of graphical programming applications or graphical programs. In one embodiment, the method provides a set of VI Server function nodes and controls which a user employs to create a client graphical program. The client executes in a computer which includes a display screen and a user input device. In one embodiment, the client performs instrumentation control functions. The user can thus create diagrams in a graphical programming system, e.g. LabVIEW, that get/set properties and invoke operations on both graphical programming applications and graphical programs (VIs) within the respective user's local version of LabVIEW as well as on other copies of LabVIEW or graphical programs on a network, such as a TCP/IP network.

Abstract: A method, apparatus, and article of manufacture for creating macro language files for executing SQL queries in a relational database management system via the World Wide Web of the Internet. In accordance with the present invention, Web users can request information from RDBMS software via HTML input forms, which request is then used to create an SQL statement for execution by the RDBMS software. The results output by the RDBMS software are themselves transformed into HTML format for presentation to the Web user.

Abstract: A technique is disclosed for efficiently placing logic cells from an electronic design during an incremental recompile. This is accomplished by fixing in place as many logic cells as possible during the recompile procedure. To understand how this works, recognize than an "original electronic design" has already been fully compiled. Now, a user has made one or more changes to the original electronic design to produce a "changed electronic design." The disclosed technique fits the changed electronic design, during incremental recompile, without effecting too much of the logic previously fit during compilation of the original electronic design. Initially, a compiler attempts to fit logic cells of the changed portion of the electronic design onto available logic elements of the hardware device while confining logic cells from the unchanged portion of the changed electronic design to their original positions.

Abstract: A core-based PLD programming method for programming a PLD to implement a user-defined logic operation including a set of cores. The PLD includes several configurable logic blocks (CLBs). Each core includes several logic portions that are arranged in a fixed pattern, and each logic portion includes configuration data for configuring one CLB. A placement process is performed during which only a single reference logic portion of each core is placed in a configuration data table to form a first placement pattern. Non-reference portions of the cores are not placed in the configuration data table during the initial placement process. An annealing process is then performed during which the reference logic portions associated with the cores are moved between CLB sites in an attempt to identify an optimal placement solution. A separate CLB site overlap table is utilized to keep track of the non-reference logic portions during the annealing process.

Abstract: A method of changing layout of a semiconductor device includes: a step of preparing a physical layout representative of a layout of circuit constituents of a semiconductor device; a step of detecting a contradictory area in the physical layout not conforming with predetermined design rule; a step of converting the physical layout into a graphical representation by extracting nodes such as a transistor and a contact and branches interconnecting nodes from the physical layout; a step of solving the contradictory area in the graphical representation by inserting a new vector into a corresponding branch; and a step of converting the final graphical representation into a new physical representation. The method can automatically solve contradictory areas of a physical layout of a semiconductor device.

Abstract: A method for optimizing layout design using logical and physical information performs placement, logic optimization and routing and routing estimates concurrently. In one embodiment, circuit elements of the integrated circuit is partitioned into clusters. The clusters are then placed and routed by iterating over an inner-loop and an outer-loop according to cost functions in the placement model which takes into consideration interconnect wiring delays. Iterating over the inner-loop, logic optimization steps improves the cost functions of the layout design. Iterating over the outer-loop, the size of the clusters, hence the granularity of the placement, is refined until the level of individual cells is reached. The present method is especially suited for parallel processing by multiple central processing units accessing a shared memory containing the design data base.

Abstract: A programmed design tool and method for determining the placement of components of a very large scale integrated circuit. The present invention is characterized by a common timing engine adapted to check front end high level timing constraints in relation to a netlist representing the circuit.

Abstract: A tool is provided that automates and expedites the ASIC design review process by allowing designers to perform a comprehensive asynchronous path design review of the circuit design HDL code. The tool operates on either an entire hierarchy or any sub-block of the circuit design. Filters are provided to allow the user to disregard known and desired synchronization circuits from the output generated by the tool. The tool provides an output that can take either of two formats, i.e. the output may be presented in a tabular form by hierarchical signal name, or it may be presented in a graphical, schematic block diagram form. In operation, the tool performs an exhaustive search of all circuits and identifies any asynchronous behavior. A user interface is provided that requires two data inputs and provides for an additional optional field. The two mandatory fields identify the location of all design files and the module at which the tool should begin its analysis.

Abstract: A system for simplifying and expediting estimation of the gate RC delay and/or the determination of transistor widths for a given gate RC delay in a CMOS inverter circuit. The system determines gate RC delay as a function of transistor width. Alternatively, appropriate transistor widths may be determined based on a desired optimum gate RC delay. An analytical expression is established to predict RC induced gate propagation delay as a function of readily available technical parameters in the early stage of design. The analytical expression has been found to describe gate RC delay in CMOS inverter circuits incorporating 0.25 micron (or even smaller) manufacturing technology.