Abstract: A system and process for logic extraction from the layout of logic blocks is described. Logic design information is extracted from a transistor level net list which is stored in a memory. The transistor level net list in turn is generated from a layout polygon database using techniques in the art. The process comprises processing the transistor level net list in the memory to define groups of transistors according to whether or not transistors in the transistor level net list are connected to a supply voltage, whether or not transistors in the transistor level net list are connected to a reference voltage and the transistor type. The groups of transistors are analyzed according to their interconnections, and their membership in groups. Finally, logic units are identified in response to the step of analyzing the groups of transistors.

Abstract: A combinational logic circuit having at least one primary input terminal and at least one primary output terminal comprises a plurality of VDDH gates having an input node and an output node and operated by a standard operating voltage and a plurality of VDDL gates having an input node and output node and operated by an operating voltage which is lower than the standard operating voltage. At least one of the VDDH gates is multiple input gate. An output node of the VDDH gate or primary input terminal operated by the standard operating voltage is connected to at least one of the input nodes of the multiple input gate. The VDDL gate or the primary output terminal operated at the operating voltage which is lower than the standard operating voltage is connected to at least one of the other input nodes of the multiple input gate through a level converter.

Abstract: A method and apparatus providing a graphical user interface (GUI) that automatically determines timing groups and path groups for a circuit representation. In a first GUI display level, the GUI displays each path group in the circuit and allows the user to change the timing constraints for each path group. In addition, the GUI indicates whether each timing group is activated by a rising or falling clock signal. In addition, the user can define subpaths of a path group. After timing analysis software has analyzed the circuit, by clicking on a timing group in the first GUI display level, the user can view a second GUI display level, which shows details of the paths in the indicated timing group. By clicking on a path in the second GUI display level, the user can view a third GUI display level, which shows a list of each of the elements in the indicated path.

Abstract: A method for selecting the state assignments of a complex programmable logic device (CPLD) to minimize power consumption. Within the CPLD, a plurality of macrocells are selected to store a corresponding plurality of state variables, wherein the number of macrocells is selected to be equal to the number of states. For each of the states, one of the macrocells is assigned to store a state variable having a first logic state, and the remaining macrocells are assigned to store state variables having a second logic state. The macrocells storing state variables having the second logic state exhibit a lower power consumption than the macrocell storing the state variable having the first logic state. In addition, each of the macrocells includes a plurality of wired logic gates, each being in a high-current state or a low-current state. The number of wired logic gates in the low-current state is maximized in the macrocells assigned to store the state variables having the second logic state.

Abstract: A system and method is disclosed for converting a polygon-based wire in an integrated circuit to an object-based wire element. In one aspect of the invention, a recognition engine attempts to recognize polygonal wires in response to a wire recognition statement. First, a polygon is located and analyzed. A path having a centerline and a width is deduced from the analysis of the polygon. The path is converted into a candidate polygon that is compared with the current polygon. If the candidate polygon is substantially similar (i.e., identity is not required) to the current polygon, then the path is used to configure an object-based wire element. The geometries of the object-based wire element are then compared to corresponding geometries in a support view. If the geometries of the layers of the wire element are entirely contained within the geometries on the respective layers of the support view, then the wire element is considered recognized. The wire element is then added to a recognized view.

Abstract: A computer implemented method for generating a layout for a set of transistors on a semiconductor chip. The method comprises the step of folding transistors of the set whose sizes exceed a predetermined maximum size. Then a list of implicitly enumerated diffusion sharing arrangements of the transistors of the set is created. The method also comprises the step of choosing an arrangement from the list that uses the least horizontal space on the chip and generating a layout of the set of transistors on the chip according to the chosen arrangement. Embodiments of the invention generate diffusion sharing arrangements that are unique with respect to transistor folds, transistor orientations, and transistor fold interlacing arrangements.

Abstract: A complete procedure for verifying register-transfer logic against its scheduled behavior in a high-level synthesis environment is provided. A new method that is both complete and practical for verification is provided. Hardware verification is known to be a hard problem and the proposed verification technique leverages off the fact that high-level synthesis--performed manually or by means of high-level synthesis software--proceeds from the algorithmic description of the design to structural RTL through a sequence of very well defined steps, each limited in its scope. Equivalence checking task is partitioned into two simpler subtasks, verifying the validity of register sharing, and verifying correct synthesis of the RYL interconnect and control. While state space traversal is unavoidable for verifying validity of the register sharing, irrelevant portions of the design are automatically abstracted out, significantly simplifying the task that must be performed by a back-end model checker.

Abstract: An apparatus and method for generating a sequence of random, repeatable events for testing a cloned device against the device from which it is derived. The invention includes elements used to double the speed at which the event generator produces the events. This allows the event generator to be used in the testing of devices, such as CPUs, which operate at relatively high clock rates.

Abstract: A data management system and method that enables acquisition, integration and management of real-time data generated at different rates, by multiple, heterogeneous incompatible data sources. The system achieves this functionality by using an expert system to fuse data from a variety of airline, airport operations, ramp control, and air traffic control tower sources, to establish and update reference data values for every aircraft surface operation. The system may be configured as a real-time airport surface traffic management system (TMS) that electronically interconnects air traffic control, airline data and airport operations data to facilitate information sharing and improve taxi queuing. In the TMS operational mode, empirical data shows substantial benefits in ramp operations for airlines, reducing departure taxi times by about one minute per aircraft in operational use, translating as $12 to $15 million per year savings to airlines at the Atlanta, Georgia airport.

Abstract: A semiconductor junction (13) is represented as a junction capacitance (21) in parallel with a junction resistance (23) and junction inductance (22). The junction capacitance, junction resistance and junction inductance are functions of the voltage across the semiconductor junction and are determined using a probability of charge stored across the semiconductor junction. Junction parameters are determined with parameter extraction processes. A circuit simulation tool is used to simulate the performance of a circuit that includes the semiconductor junction. Accordingly, diode junctions are more accurately modeled above their built-in potential and below their reverse break-down voltage.

Abstract: Signal delay and skew within an integrated circuit are minimized when 1) signals are distributed to distant points of an integrated circuit via a layer of its package, and 2) traces in the package layer are etched and treated as transmission lines. As disclosed herein, a signal is driven through a first connection between an integrated circuit and an integrated circuit package layer. The signal is then distributed to one or more additional connections between the integrated circuit and the integrated circuit package layer, by means of point-to-point transmission lines formed in the integrated circuit package layer, each of the transmission lines being terminated at one or both ends by impedances which are substantially matched to the characteristic impedance of the transmission line to which they are attached. The signal is then received into the integrated circuit through the one or more additional connections between the integrated circuit and the integrated circuit package layer.

Abstract: A method is presented of generating data on component arrangement capable of shortening the moving distance of the mounting head in an electronic component mounting machine, and enhancing the mounting efficiency.The distribution center coordinates and their distributed state values of electronic components on a circuit board grouped in accordance with their kind are determined. The arrangement position of each electronic component at a component feed section is determined based on the distribution center coordinates. When the arrangement positions of more than two kinds of electronic components thus determined are the same, the arrangement position of the electronic component having a smaller distributed state value is preferentially determined.

Abstract: An integrated circuit identification device (ICID) to be incorporated into an integrated circuit (IC) includes an array of electronic cells in which the magnitude of an output signal of each cell is a function of randomly occurring parametric variations which vary from cell-to-cell. The ICID also includes a circuit for measuring the output of each cell and for producing output data having a value reflecting the particular combination of measured characteristics of all of the elements of the array. When we make the number of elements in the array large enough, we insure that to a high degree of probability, the pattern of measured array cell characteristics for an ICID embedded in any one IC will be unique and distinguishable from such patterns measured by ICIDs embedded in millions of other ICs. Thus the value of the output data produced by an ICID circuit acts as a unique "fingerprint" for the IC in which it is installed, and can be used as a unique identification (ID) for that IC.

Abstract: A disassembly route producing apparatus searches for a disassembly route for disassembling a product into its component parts. In one embodiment, the apparatus selects one of the parts to be disassembled, and determines the closest distance the selected part may approach the remaining parts as the selected part is being moved. The selected part is disassembled through a series of translations in predetermined directions and for predetermined distances. After each translation, the apparatus determines whether the selected part collided with any of the remaining parts. If a collision occurs, the apparatus changes the direction for the translations and resumes the search. A corresponding assembly route is determined by reversing the disassembly route.

Abstract: An object of the present invention is to provide for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.

Abstract: A hierarchical layout designing method for an LSI has the step of determining the layout positions and shapes of hard macro blocks and a soft macro block, the step of forming a wiring which connects the hard macro blocks to each other and a path which passes above the soft macro block, the step of evaluating the influence which a wiring passing above the soft macro block will influence on the internal wiring of the soft macro block, a determination step of determining the extending direction in which the cell rows are to extend in the soft macro block, the step of forming in the soft macro block the cell rows in which cells are to be placed, and the step of calculating a first cost "COST x" in the case where the cell rows are formed extending in an x-axial direction and a second cost "COST y" in the case where the cell rows are formed extending in any-axial direction.

Abstract: An efficient method for determining the periodic steady state response of a circuit driven by a periodic signal, the method including the steps of 1) using a shooting method to form a non-linear system of equations for initial conditions of the circuit that directly result in the periodic steady state response; 2) solving the non-linear system via a Newton iterative method, where each iteration of the Newton method involves solution of a respective linear system of equations; and 3) for each iteration of the Newton method, solving the respective linear system of equations associated with the iteration of the Newton method via an iterative technique. The iterative technique may be a matrix-implicit application of a Krylov subspace technique, resulting in a computational cost that grows approximately in a linear fashion with the number of nodes in the circuit.

Abstract: A set of software programs on a client computer is compared against a set of updates on a server computer to determine which updates are applicable and should be transferred from the server to the client. If the link between the client and server is slow, the listing of available updates must be represented in compact form. A many-to-one mapping function (e.g. a hash function) is applied to update identifiers to generate a table of single bit entries indicating the presence of particular updates on the server. This table is transferred to the client over the slow link. At the client, the same mapping function is applied to program identifiers, and corresponding entries of the transferred table are checked to determine whether the server has a potential update. If such a potential update is noted, a second transmission is requested by the client from the server--this one conveying additional data by which hash collisions can be identified by the client and disregarded.

Abstract: A method and apparatus for lowering the power dissipation for a semiconductor IC without adverse effects on its operation. The method takes into consideration the timing and function of the IC. The methods includes an analysis step to determine the delay time of each logic path by using test patterns, a classifying step for the logic paths corresponding to the delay times on the logic paths, a marking step for a class mark of the group classified in the classifying step to nodes of each logic path, a shrinking step for reducing the size of an element or a basic cell connected to the nodes having the mark of the smaller delay time group in the classified groups, and a confirming step for the delay times on the logic paths.

Abstract: Automatic generation of gate-level descriptions from table-based descriptions within the field of electronic design automation. The gate-level and structural descriptions are used for test generation processes and some formal verification processes. For combinational table-based descriptions, ordered ternary decision diagram (OTDD) graphs are used with novel input reordering to extract prime, non-redundant cube sets that can include high level functions (e.g., XOR, XNOR, MUX). For sequential table-based descriptions, a reduced or "clock" based OTDD graph is generated from which data and clock signals are identified and characterized. Input reordering is done and a complete sequential OTDD graph is generated, followed by port separation and characterization of the sequential element. Clock and data functions are then constructed on a port-by-port basis using the prime, non-redundant cube set generation processes of the combinational logic phase.