Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.

Abstract: A Point-Of-Sale (POS) processing environment is encapsulated within a container running on a first Operating System (OS) of a transaction terminal. Peripheral drivers for connected peripherals run on a second and different OS of the transaction terminal. A platform processing environment runs the peripheral drivers on the second and different OS of the terminal. A socket interface is provided for communication between transaction applications of the POS processing environment with the peripheral drivers of the platform processing environment for purposes of allowing the transaction applications to control and access the connected peripherals during transactions performed at the transaction terminal via the socket interface.

Abstract: Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.

Abstract: A new approach is proposed to support hardware-based PCIe link up based on post silicon characterization of an electronic device. A non-volatile storage medium of a bootup unit on the electronic device maintains an initialization sequence for the physical layer of a PCIe link, and a non-volatile storage medium allows flexible programming. During operation, the bootup unit reads from the non-volatile storage medium instructions to program/override one or more PCIe physical layer settings and controller registers for the PCIe link based on the post silicon characterization of the electronic device. The bootup unit is limited to access and override only to the one or more physical layer settings and controller registers of the PCIe link. The entire process of reading the initialization sequence and programming the one or more PCIe physical layer settings and the controller registers happens within time limit constraints of the PCIe specification for latency reduction.

Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.

Abstract: In accordance with an embodiment, an integrated driver circuit includes: a first connection and a second connection configured to be connected to a control chip; at least one bus connection configured to be connected to a bus line; and a control circuit. The control circuit is configured to operate in a first mode or a second mode; to output a reception signal at the second connection in the second mode, where the reception signal represents a bus signal received at the bus connection; to assume a state of low power consumption in the first mode; to change from the first mode to the second mode when a first command is detected at the first connection or at the second connection; and to change from the second mode to the first mode when the bus signal does not indicate any data for a predefined period of time.

Abstract: An information processing apparatus includes a storage unit configured to store at least a first boot program and a second boot program corresponding to the first boot program, a controller configured to read and execute a program, detect, in accordance with occurrence of a read error at reading of the first boot program, an address of a storage area storing a program in which the read error has occurred in the first boot program, and specify, from an address of a storage area storing the second boot program, an address corresponding to the detected address. The controller reads and executes the second boot program stored in the specified address.

Abstract: Systems and methods are provided for the deterministic simulation of distributed systems, such as vehicle-based processing systems. A distributed system may be represented as a plurality of subsystems or “nodelets” executing with a single process of a computing device during a simulation. A simulated clock may be used during execution of the nodelets to mitigate the variability in timestamped data that may be caused by latency or jitter. In some embodiments, all timestamps generated during a given frame of work will be assigned the same time value, regardless of when within the frame the timestamps were generated. A task scheduler can update the value of the simulated clock as execution proceeds through different frames of work.

Abstract: A method and apparatus for data storage devices, or other devices that are L1 sub-state capable, to enter these sub-states while on the same network or bus as a device not enabled for transition to an L1 power sub-state. According to certain embodiments, a PCI FW register is configured to place a CLKREQ de-assert signal to a MAC of the data storage device, independent of the power state of the host. The CLKREQ de-assert signal causes the MAC to place the data storage device in an L1 power substate such as L1.2. A sensor of the controller remains active to detect a wakeup signal from the host that causes the data storage device to transition to a higher power state.

Abstract: Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.

Abstract: A method and a system for filtering process I/O operations are provided herein. The system may include: a memory component configured to store computer implementable instructions; and, a processor configured to implement the computer implementable instructions, such that the system is arranged to: determine that a process is queued for initiation on the system; correlate the process with one or more predefined policies; and filter the process by blocking or permitting the process from completing I.O operations on the system according to the one or more predefined policies, wherein the computer implementable instructions are implemented in a kernel-mode of the system.

Abstract: Novel techniques are described for operating system (OS) agnostic containerization for application deployment. For example, an application is being deployed to a large number of target computational environments running a variety of different OSs, including OSs that are either unknown to the deployment environment or not directly supported by OS-specific container runtimes accessible to the deployment environment. Embodiments can automatically generate a resource profile of a target OS running in a target computational environment, for example, by exploiting functionality of a network interface application also running in the target computational environment. The resource profile can be used to convert an OS-agnostic container runtime into a target-tailored container runtime (tailored for the target OS), and the target-tailored runtime can be deployed to build the containerized application in the target computational environment.

Abstract: The invention introduces a method for producing solid state disk (SSD) devices, performed by a processing unit of a production host, to include steps of: loading a port-mapping configuration table including location information regarding each port connected to the production host; comparing location information in a hardware description file with the location information in the port-mapping configuration table to determine which ports that SSD devices are connected to; displaying a graphical user interface (GUI) on a displayer to indicate which ports are connected by SSD devices; and when an SSD device connected to one port that fails to activate, updating the GUI to display information indicating that an SSD device connected to the corresponding port that fails to activate.

Abstract: Replaceable print material supply cartridges for printers are disclosed herein. An example replaceable print material supply cartridge includes logic circuitry that is to determine a position of the replaceable print material supply cartridge by initiating a first voltage on a data contact during a time period, monitoring a timer without reference to a clock signal at a clock contact from a serial data bus, and maintaining a first voltage on the data contact for a duration of time. After expiration of the duration, the logic circuitry is to cause the data contact to assume a second voltage, different than the first voltage, and the logic circuitry is to read data from the memory and cause transmission of a data signal via the serial data bus interface.

Abstract: A logic circuitry package for a replaceable print apparatus component includes an interface to communicate with a print apparatus logic circuit, and at least one logic circuit to transmit, via the interface, a sensor ID parameter and a limit parameter, the sensor ID parameter indicating a first sensor ID. The logic circuit is to receive, via the interface, a first request corresponding to the first sensor ID with the component connected to the apparatus and the apparatus not pneumatically actuating the component. The logic circuit is to transmit, via the interface, a first digital value in response to the first request. The logic circuit is to receive, via the interface, a second request corresponding to the first sensor ID with the component connected to the apparatus and the apparatus pneumatically actuating the component. The logic circuit is to transmit, via the interface, a second digital value in response to the second request.

Abstract: A digital processing system including a master chip having a first clock pin and a first data pin and a first slave chip having a second clock pin and a second data pin may be provided. The digital processing system may transmit first data from the master chip to the first slave chip based on a synchronous scheme in which a first clock signal output from the master chip via the first clock pin and the first data output from the master chip via the first data pin are provided together and the first data is transmitted in synchronization with the first clock signal, and may transmit second data from the first slave chip to the master chip based on an asynchronous scheme in which the second data output from the first slave chip via the second data pin is transmitted regardless of the first clock signal.

Abstract: Power delivery may be controlled to help prevent arcing when a data cable supplying power from a power source device to a power sink device is disconnected. The presence of a user in proximity to a connection between a cable plug and a cable receptacle may be detected. The level of a power signal being conveyed from the power source to the power sink may be reduced in response to the detection.

Abstract: Computing clusters can be automatically configured according to some aspects described herein. For example, a system can receive configuration datasets from instantiated objects in a management cluster. The configuration datasets can be for configuring target objects in managed clusters, where the managed clusters are separate from the management cluster. The system can then configure the target objects within each of the managed clusters based on the configuration datasets.

Abstract: A coordinated initialization system includes a computing system with first and second initialization subsystems coupled to a coordinated initialization subsystem. The coordinated initialization subsystem receives first and second initialization progress information associated with respective first and second initialization subsystem operations performed by the respective first and second initialization subsystems.

Abstract: Methods and apparatuses for improve clocking scheme to reduce power consumption are presented. The apparatus includes a host configured to communicate with a memory via a link. The host is further configured to receive a first clock from the memory; to receive, based on the first clock, data from the memory, in a first mode of a read operation; to generate a second clock, the second clock being generated independent of the first clock; and to receive, based on the second clock, data from the memory, in a second mode of the read operation.