Abstract: A heuristic solver is wrapped in a meta algorithm that will perform multiple sub-runs within the desired time limit, and expand or reduce the effort based on the time it has taken so far and the time left. The goal is to use the largest effort possible as this typically increases the probability of success. In another implementation, the meta algorithm iterates the time-like parameter from a small value, and determine the next test-value so as to minimize time to target collecting data at large effort only as necessary. The meta algorithm evaluates the energy of the solutions obtained to determine whether to increase or decrease the value of the time-like parameter. The heuristic algorithm may be Simulated Annealing, the heuristic algorithm may run on a quantum processor, including a quantum annealing processor or a gate-model quantum processor.

Abstract: A method for optimizing energy consumption of a computing infrastructure comprising a plurality of compute nodes, each associated with a plurality of jobs. The method includes receiving an energy consumption reduction request comprising an energy consumption reduction objective; determining a set of jobs to be suspended; and sending, to a runtime environment of each compute node associated with a job comprised in the determined set of jobs, a suspension request comprising said job. Upon receiving the suspension request, the method includes suspending the job comprised in the received suspension request, the suspension being carried out via a set of non-native instructions implemented in the runtime environment of each compute node; and active waiting by the suspended job for a suspension stop message comprising said suspended job, the active waiting being carried out via a set of non-native instructions implemented in the runtime environment of each compute node.

Abstract: The present invention provides a system and method for optimizing BOM cost of platform SoC for Battery management system. The system (100) comprises a sensor (101), coupled with the device to receive input physical parameters Temperature, Voltage and current and a CPU with SIMD extensions without saturation logic in the instruction set and floating-point unit, wherein Battery management module is implemented (101). Using CPU with SIMD extensions instead of DSPNLIW core in platform SoC helps in lowering the BoM cost and the inventive steps helps in achieving bit-exact results overcoming the limitations of CPU ISA as against DSP ISA. The power consumed in either case (Battery management implementation on CPU, DSP ISA) is the same, thus giving value additions to platform SoC designers and makers.

Abstract: Examples include techniques to reduce memory power consumption during a system idle state. Cores of a single socket multi-core processor may be mapped to different virtual non-uniform memory architecture (NUMA) nodes and a dynamic random access memory (DRAM) may be partitioned into multiple segments that are capable of having self-refresh operations separately deactivated or activated. Different segments from among the multiple segments of DRAM may be mapped to the virtual NUMA nodes to allow for a mechanism to cause memory requests for pinned or locked pages of data to be directed to a given virtual NUMA node.

Abstract: Systems and methods for opening files on a client device include receiving a request to open a file and identifying a file type pertaining to the file. A list of software applications is identified that are capable of opening the identified file type, and metadata pertaining to each of the software applications on the list is retrieved. User preference data pertaining to a user requesting to open the file is also retrieved. Scores for the software applications on the list are then determined based at least on the metadata and the user preference data. At least one software application on the list is then selected to open the file on the client device based on the determined scores.

Abstract: An eUSB repeater is described for passing repeating mode packets between a differential bus and a single-ended bus. An eUSB transceiver is coupled to a single ended bus, a USB transceiver is coupled to a differential bus, and repeater logic is coupled to and between the eUSB transceiver and the USB transceiver. A first enable control circuit receives a digital state transition from the differential data bus and generates an enable signal to an analog single-ended transmitter of the eUSB transceiver. A second enable control circuit receives a digital state transition from the single-ended data bus and generates an enable signal to an analog differential transmitter of the USB transceiver.

Abstract: Devices, methods, and systems are provided. In one example, a device is described to include a device interface that receives data from at least one data source; a data shuffle unit that collects the data received from the at least one data source, receives a descriptor that describes a data shuffle operation to perform on the data received from the at least one data source, performs the data shuffle operation on the collected data to produce shuffled data, and provides the shuffled data to at least one data target.

Abstract: Systems and methods are provided that may be implemented to dynamically change the solid state drive (SSD) power and peripheral component interconnect express (PCIe) link state transition time for solid state drive for SSD operation based on current remaining battery power capacity during a battery-only power mode of an information handling system. In one example, an intelligent algorithm in software and SSD firmware may be implemented that will dynamically change the SSD power and PCIe link state transition based on current remaining battery power capacity during battery-only power mode of an information handling system. In this way additional power saving may be realized when current remaining battery power capacity is low during a battery-only power mode so as to extend the battery life for an information handling system.

Abstract: Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

Abstract: According to an aspect, there is provided a solution for providing an access to a slave unit. An address from a master unit trying to access a slave unit is received (400). The received address is mapped (402) to a slave address. Default access permissions are associated (404) to the master-slave connection. Additional access permissions associated with the master unit and the slave address are determined (406). The master-slave connection is enabled (408) if additional access permissions allow the master unit to access the slave, otherwise the connection is rejected.

Abstract: A storage system is provided. The storage system includes a plurality of storage units, each having a controller and solid-state storage memory. The storage system further includes one or more first pathways that couple processing devices of a plurality of storage nodes and is configured to couple to a network external to the storage system and one or more second pathways that couple the plurality of storage nodes to the plurality of storage units, wherein the one or more second pathways enable multiprocessing applications.

Abstract: A method for controlling operation of a mobile first Edge Computing, EC, server (220) configured to provide compute resources to User Equipment, UE, (303), wherein the first EC server is connected to an EC management entity (300) configured to manage a plurality of EC servers (220, 220-2), the method being carried out in the first EC server and comprising receiving (501) status information associated with the first EC server from an external entity; receiving (500,503) control information from the EC management entity, said control information identifying a power state control instruction; determining (504) a power state triggering event in accordance with the power state control instruction, based on the received status information; controlling (506) the power state of the first EC server responsive to the determined power state triggering event.

Abstract: The communication system according to one embodiment for an elevator comprises a bus controller and a plurality of bus nodes. The bus controller periodically sends requests to all bus nodes and receives the responses from the bus nodes. The bus nodes receive requests from the bus controller and send responses to the bus nodes. The bus controller is designed to select a group of bus nodes for each of its requests and to wait for the responses of these bus nodes between two requests.

Abstract: A low voltage drive circuit (LVDC) includes a digital to analog input circuit to convert transmit digital data into combined analog outbound data, the transmit digital data has a data rate based on a host input clock, and a first portion of the combined analog outbound data has a first oscillation rate based on a first transmit channel clock and a second portion has a second oscillation rate based on a second transmit channel clock. The LVDC also includes a drive sense circuit to convert the combined analog outbound data into an analog transmit signal that is transmitted on a bus. The LVDC also includes a clock circuit to generate a transmit input clock to synchronize receiving the transmit digital data from a host, generate the first transmit channel clock based on the host input clock, and generate the second transmit channel clock based on the host input clock.

Abstract: A transceiver device includes a transmitter and a receiver connected to each other through a first line and a second line. The transmitter transmits signals having a first voltage range to the first line and the second line in a first mode, and transmits signals having a second voltage range less than the first voltage range to the first line and the second line in a second mode. The transmitter encodes an original payload to generate a first payload in the second mode, and transmits a clock training pattern and the first payload through the first line and the second line. The receiver decodes the first payload and outputs reception data corresponding to the original payload in the second mode.

Abstract: Systems and methods are disclosed for reducing power consumed by capturing data from an I/O device. Techniques disclosed include receiving descriptors, by a controller of an I/O host of a system, including information associated with respective data chunks to be captured from an I/O device buffer of the I/O device. Techniques disclosed further include capturing, based on the descriptors, the data chunks. The capturing comprises pulling the data chunks from the I/O device buffer at a pulling rate, where the data chunks are transferred to a local buffer of the I/O host, and pushing segments of the pulled data chunks from the local buffer, where each segment is transferred to a data buffer of the system after a respective target time that precedes a time at which the data chunks in the segment are to be processed by an application executing on the system.

Abstract: Disclosed is a clock multiplexing circuit which includes a first transistor that is between a first input terminal that receives a first input clock signal and an output terminal that outputs an output pulse signal and operates based on a logic level of a second input terminal receiving a second input clock signal, and a second transistor that is between the output terminal and a first voltage node and operates based on the logic level of the second input terminal. The first input clock signal and the second input clock signal have the same period and have different phases. The output pulse signal transitions to a first logic level at a first time when the first input clock signal transitions to the first logic level and transitions to a second logic level at a second time when the second input clock signal transitions to the first logic level.

Abstract: Aspects relate to limits management for a processor power distribution network. In an aspect, an electronic device has a processor with a processing core that is coupled to a power rail. The power rail is external to the processor. A current sensor is associated with the output of the power rail and configured to produce current sensor readings. A state-space unit is coupled to the current sensor. The state-space unit has a predictive model to apply the current sensor readings to the predictive model to predict a current budget for the processing core. A limit manager is configured to generate a current limit in response to the current budget. The limit manager limits a current draw of the processing core in response to the current limit.

Abstract: An exemplary method includes accessing information associated with a power supply connection between a plurality of power distribution units and a plurality of power converters of a data center appliance, determining, based on the information, a current power connection topology of the plurality of power converters of the data center appliance with respect to the plurality of power distribution units, analyzing the current power connection topology to determine whether the current power connection topology satisfies predefined operating parameters for the data center appliance and the plurality of power distribution units, and performing, based on the analyzing of the current power connection topology, an action associated with the power supply connection between the plurality of power converters and the plurality of power distribution units.

Abstract: A hashboard, a power supply system of a digital processing device and the digital processing device. The digital processing device comprises: a housing; N (?2) hashboards and a control board both located inside the housing. Each hashboard comprises: a substrate; power positive and power negative terminals respectively mounted on the substrate and adapted to be connected to another hashboard in series; a communication interface mounted on the substrate; and computing chips mounted on the substrate. A signal transfer path of the computing chips has a chain configuration. The N hashboards are connected in series to form a series power supply configuration, a power positive terminal of a first hashboard in the series power supply configuration is connected to a positive terminal of a power supply, and a power negative terminal of a last hashboard in the series power supply configuration is connected to a negative terminal of the power supply.