Patents Examined by Paul R. Myers
  • Patent number: 11226650
    Abstract: A system for managing a time reference includes a real-time clock, an interface, and a processor. The real-time clock store an RTC time. The interface is configured to receive a GPS time and a cellular time. The processor is configured to: indicate to start a time-speed adjustment loop; determine a true time based at least in part on the GPS time and the cellular time; determine an error between the true time and the RTC time; determine an RTC speed calibration adjustment based at least in part on the error; and adjust the real-time clock speed based at least in part on the RTC speed calibration adjustment.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: January 18, 2022
    Assignee: Lytx, Inc.
    Inventor: Bernd Egler
  • Patent number: 11221980
    Abstract: A low voltage drive circuit (LVDC) operable to convey data via a bus and includes a signal generator operable to convert transmit digital data into analog outbound data. The LVDC also includes an analog to digital output circuit operable to convert analog inbound data into received digital data. The LVDC further includes a drive circuit operable to convert the analog outbound data into an analog transmit signal and drive the analog transmit signal on to the bus, where the analog outbound data is represented within the analog transmit signal as variances in loading of the bus at a first frequency. The LVDC further includes a sense circuit operable to receive an analog receive signal from the bus and convert the analog receive signal into the analog inbound data, where the analog inbound data is represented within the analog receive signal as variances in loading of the bus at a second frequency.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 11, 2022
    Assignee: SIGMASENSE, LLC.
    Inventors: Richard Stuart Seger, Jr., Daniel Keith Van Ostrand, Gerald Dale Morrison, Timothy W. Markison
  • Patent number: 11222120
    Abstract: A method includes receiving an indicator at a basic input/output system of an information handling system, the indicator identifying that validation of a boot loader at a non-volatile memory at a data storage device failed authentication. The boot loader is configured to identify application layer firmware at the data storage device. The method further includes retrieving a replacement boot loader from a predetermined storage location and providing the replacement boot loader to a baseboard management controller (BMC). The method further includes transmitting the replacement boot loader to the data storage device via a serial interface other than a primary interface configured to support access of user data at the data storage device.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 11, 2022
    Assignee: Dell Products L.P.
    Inventors: Simon Kan Lip Vui, Nicholas D. Grobelny
  • Patent number: 11216282
    Abstract: A booting technology for a multi-die and multi-core computing platform is shown. A storage device stores number 1 firmware code and number 0 firmware code. A master die is coupled to the storage device through a bus and accesses the number 1 firmware code from the storage device through the bus. A first slave die is also coupled to the storage device through the bus. However, instead of accessing the storage device for the number 1 firmware code, the first slave die monitors the bus and retrieves the number 1 firmware code, accessed by the master die, from the bus. The master die further accesses the number 0 firmware code from the storage device through the bus. The master die executes the number 0 firmware code to operate the master die and the first slave die to boot the system and start up the platform.
    Type: Grant
    Filed: July 8, 2020
    Date of Patent: January 4, 2022
    Assignee: SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
    Inventors: Qunchao Feng, Yankui Niu, Jinglong Liu, Yongfeng Song, Jiangbo Wang, Jintao Wang
  • Patent number: 11216047
    Abstract: The present disclosure relates to a system for at least one of identifying or verifying which specific data center device, from a plurality of data center devices, is being powered from an AC outlet of a power distribution unit. The system includes a message encoding algorithm module, a message decoding algorithm module and an input signal monitoring subsystem. The input signal monitoring subsystem monitors an AC power signal being supplied to the data center devices, wherein one of the data center devices includes an AC powered target device. A power distribution unit (PDU) supplies the AC power signal to the AC powered target device. The PDU has a controller which uses the message encoding algorithm to create a modulated AC power signal that includes an encoded message in accordance with a predetermined power cycle profile (PCP) event. The target device analyzes the PCP event as the modulated AC power signal is received and creates a decoded message therefrom.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: January 4, 2022
    Assignee: Vertiv IT Systems, Inc.
    Inventors: Kevin R. Ferguson, Steven Geffin
  • Patent number: 11210252
    Abstract: A processor executes firmware to write control data describing transfer descriptors for a bus protocol engine to an address that is associated with a transfer descriptor buffer for the bus protocol engine. The bus protocol engine performs an operation according to the transfer descriptors with a slave device; the processor is part of a first semiconductor package; the bus protocol engine is part of a second semiconductor package other than the first semiconductor package; and the address corresponds to a memory of the second semiconductor package. A first physical interface of the first semiconductor package communicates with a second physical interface of the second semiconductor package to direct the control data to the memory.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: December 28, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Naysen J. Robertson, Robert L. Noonan, David F. Heinrich
  • Patent number: 11204888
    Abstract: A circuit for receiving serial data. In some embodiments, the circuit has an input for receiving an analog input signal, and includes a first sampler for sampling the analog input signal relative to a first reference voltage, a second sampler for sampling the analog input signal relative to a second reference voltage, and a reference voltage control circuit. The second reference voltage may have a sign opposite to that of the first reference voltage; and the reference voltage control circuit may be configured to adjust the first reference voltage or the second reference voltage, based on a first sample of the analog input signal, the first sample having been taken at a sampling time corresponding to a one bit, in the serial data, preceded by a one bit and followed by a one bit.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: December 21, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Amr Khashaba, Amir Amirkhany
  • Patent number: 11200190
    Abstract: Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: December 14, 2021
    Assignee: Innogrit Technologies Co., Ltd.
    Inventors: Gang Zhao, Wei Jiang, Jie Chen, Lin Chen
  • Patent number: 11194751
    Abstract: An apparatus, such as a re-driver, can include a receiver port coupled to a first link partner across a first link; a transmitter port coupled to a second link partner across a second link; and a power management (PM) controller implemented in hardware. The PM controller can detect a PM control signal, determine a PM state for the apparatus based on the PM control signal, and cause the apparatus to enter the PM state. The apparatus can transmit electrical signals to the second link partner based on the PM state. The PM management control signal can include a clock request, an electrical idle, a common mode voltage, or other electrical signal indicative of a PM link state change of a link partner coupled to the re-driver.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Huimin Chen, Jingbo Li, Kai Xiao, Yong Yang, Chunfei Ye
  • Patent number: 11182318
    Abstract: Embodiments of the present disclosure provide an interrupt controller in a processor, comprising: an interrupt sampling circuitry configured to receive one or more interrupts from one or more interrupt sources that are communicatively coupled to the interrupt controller; and an arbitration circuitry configured to select a to-be-responded interrupt from the received one or more interrupts, the arbitration circuitry comprising: a selection circuitry configured to select from the one or more interrupts a highest-priority interrupt that has a highest priority among the one or more interrupts; and a threshold comparison circuitry communicatively coupled to the selection circuitry, the threshold comparison circuitry configured to compare the priority of the highest-priority interrupt with a preset priority threshold, wherein the arbitration circuitry is configured to select the highest-priority interrupt as the to-be-responded interrupt in response to the threshold comparison circuitry determining that the priority
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: November 23, 2021
    Assignee: Alibaba Group Holding Limited
    Inventors: Chaojun Zhao, Xiaoyan Xiang, Chen Chen, Taotao Zhu
  • Patent number: 11150716
    Abstract: Various embodiments are provided for providing optimized margins of processors in a computing environment. Margins of voltage, frequency, or a combination thereof may be dynamically monitored and adjusted for a executing a processor based a workload scheduled during an event.
    Type: Grant
    Filed: February 5, 2020
    Date of Patent: October 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Preetham M. Lobo, Pradeep Bhadravati Parashurama, Tobias Webel, Ramon Betran Monfort, Alper Buyuktosunoglu
  • Patent number: 11144492
    Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: October 12, 2021
    Assignee: Intel Corporation
    Inventors: Debendra Das Sharma, Michelle C. Jen, Prahladachar Jayaprakash Bharadwaj, Bruce A. Tennant, Mahesh Wagh
  • Patent number: 11138019
    Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding constraints to the routing graph based on an architecture of the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC based on the routing graph, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: October 5, 2021
    Assignee: XILINX, INC.
    Inventors: Akella Sastry, Henri Fraisse, Rishi Surendran, Abnikant Singh
  • Patent number: 11137823
    Abstract: The present disclosure describes methods and systems for data storage or other devices that are L1 sub-state capable, to be able to enter these sub-states while on the same network or bus as a device not enabled for transition to an L1 sub-state. In some embodiments, when an LTSSM circuit in a MAC of a PCIe device indicates an L1 idle state, an L1 sub-state (L1SS) timer is initiated in a CLKREQ on the device. Upon expiration of the timer, a CLKREQ_in emulator de-asserts its signal on the MAC, causing the MAC to enter an L1SS.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 5, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Elkana Richter, Shay Benisty, Nissim Elmaleh
  • Patent number: 11132044
    Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area, and an address of the first P2L data structure can be stored in the second P2L data structure.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Giuseppe D'Eliseo, Xiangang Luo, Ting Luo, Jianmin Huang
  • Patent number: 11126580
    Abstract: An input/output (I/O) and control system for long distance communications and industrial applications is provided having a two wire bus and bus protocol for communications between field devices and a channel generator for monitoring and control of the field devices. The channel generator produces an offset square wave on the bus, and sends a synchronization pulse of selected duration at the start of each bus scan cycle in a pulse train cycle to reset counters in the field devices before the bus scan cycle is repeated, to ensure field devices are synchronized, transmitters transmit on the correct channel, and receivers sample the pulse cycle at the correct time. High side and low side current detectors for respective ones of the two wires of the bus and an algorithm are provided to improve detection of valid inbound transmissions by the channel generator for increased noise immunity.
    Type: Grant
    Filed: February 4, 2020
    Date of Patent: September 21, 2021
    Assignee: Hubbell Incorporated
    Inventors: Nik Ilijic, Andrew Rhydian Jones
  • Patent number: 11119958
    Abstract: A hybrid bus apparatus is provided. The hybrid bus apparatus includes a hybrid bus bridge circuit configured to couple a master(s) with one or more auxiliary slaves via heterogeneous communication buses. The hybrid bus bridge circuit and the auxiliary slaves are associated with respective unique slave identifications (USIDs). The master(s) can only support a fixed number of the USIDs, and thus a fixed number of the auxiliary slaves. The hybrid bus bridge circuit is configured to opportunistically mask some or all of the auxiliary slaves such that the respective USIDs associated with the masked auxiliary slaves can be reused by the master(s) to support additional slaves. As such, it may be possible to extend the capability of the master(s) to support more slaves than the fixed number of USIDs the master(s) can provide, thus enabling flexible heterogeneous bus deployment in an electronic device incorporating the hybrid bus apparatus.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 14, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Christopher Truong Ngo, Alexander Wayne Hietala
  • Patent number: 11113220
    Abstract: A single-wire peer-to-peer (P2P) bus apparatus is provided. The single-wire P2P bus apparatus includes a first peer device and a second peer device(s) coupled to a single-wire bus that correspond to a first bus access priority and a second bus access priority(s), respectively. Any of the first peer device and the second peer device(s) can contend for access to the single-wire bus by asserting a bus contention indication(s) when the single-wire bus is in a defined bus state. A winner for the single-wire bus may be a peer device having a highest bus access priority among those peer devices asserting the bus contention indication(s). In this regard, any peer device on the single-wire bus can have a chance to initiate communications over the single-wire bus, thus making it possible for the single-wire bus to function based on bidirectional P2P bus architecture capable of supporting more application and/or deployment scenarios.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: September 7, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Christopher Truong Ngo, Nadim Khlat, Alexander Wayne Hietala
  • Patent number: 11113221
    Abstract: A mode switching system including a first electronic device and the second electronic device is provided. The first electronic device includes a main control unit, a USB Type-C interface controller and a USB hub. The interface controller is coupled to the main control unit. The USB hub is coupled to the interface controller. The second electronic device is coupled to the interface controller of the first electronic device. The main control unit is configured to: (1) disable the USB hub in response to a mode switching instruction; (2) switch the mode of the interface controller from a first mode to a second mode; (3) command the interface controller to re-communicate with the second electronic device.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: September 7, 2021
    Assignee: Qisda Corporation
    Inventor: Sheng-Hsiang Hsieh
  • Patent number: 11073893
    Abstract: The invention provides a system capable of remotely controlling electronic apparatus. The system comprises a cloud management platform and an electronic apparatus. The electronic apparatus comprises a motherboard and a data storage device. The motherboard comprises a standby power circuit. A standby power is supplied to the data storage device via the standby power circuit. The data storage device comprises a data storage unit and a program management unit. The program management unit comprises a microprocessor and a network communication component. Whether the electronic apparatus is in a power-on state or a power-off state, the data storage device can always maintain in a normal operation via the standby power. When the microprocessor of the program management unit receives a specific operation instruction from the cloud control platform, it will execute a corresponding operation program according to the specific operation instruction.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: July 27, 2021
    Assignee: Innodisk Corporation
    Inventor: Chih-Ching Wu