Patents Examined by Paul R. Myers
  • Patent number: 11914536
    Abstract: The device described herein, which provides an interface between a plurality of master devices and a slave device, includes: a first timer configured to begin timing when a first access request is received from a first master device via a bus, and to be reset when a semaphore is allocated to the first master device; a second timer configured to begin timing when a second access request is received from a second master device via the bus, and to be reset when a semaphore is allocated to the second master device; and a controller configured to provide a first message to the first master device via the bus when a first expiration interval is measured by the first timer.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: February 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Dongsik Cho
  • Patent number: 11907771
    Abstract: Disclosed are an action recognition device and an action recognition method for recognizing actions of multiple objects in real time. The action recognition device includes a camera for capturing an image, a target queue storing therein data about at least one target, a reasoner configured to perform action reasoning, and a computing device electrically connected to the camera, the target queue and the reasoner, wherein the computing device may update the target queue based on an object tracking result on the image, extract a target from the target queue, request the reasoner to perform action reasoning on the extracted target, and output an action recognition result based on an action reasoning result provided from the reasoner.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: February 20, 2024
    Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION
    Inventors: Young Chul Yoon, Hyeon Seok Jung
  • Patent number: 11880331
    Abstract: Methods, systems, and computer readable media can be operable to facilitate a testing of an unknown USB supply that is connected to a CPE (customer premise equipment) device to determine a current draw capacity of the USB supply. The CPE device may test the USB supply to determine whether the USB supply is capable of supplying a predetermined current. If the determination is made that the USB supply is not able to supply the predetermined current, an end-user may be instructed to plug an alternative PSU (power supply unit) into the CPE device, wherein the alternative PSU is capable of supplying the predetermined current to the CPE device. The CPE device may output an indication that an alternative PSU should be used via a graphics output to a display device through an HDMI (high-definition multimedia interface) connection or via an LED indication using one or more LEDs at the CPE device.
    Type: Grant
    Filed: September 7, 2022
    Date of Patent: January 23, 2024
    Assignee: ARRIS ENTERPRISES LLC
    Inventors: Antony J. Bristow, Adrian K Woodhouse
  • Patent number: 11875156
    Abstract: Embodiments of systems and methods for the centralized configuration of distributed heterogeneous services is disclosed herein. Embodiments of such systems and methods may be utilized to configure one or more service instances executing in an enterprise computing environment where each of the set of service instance is one of a set of service types that may be different. These services may, for example, be off-cloud services associated with a cloud based computing platform.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: January 16, 2024
    Assignee: OPEN TEXT HOLDINGS, INC.
    Inventors: Kancharla Anil Kumar, Syed Nasir Bellary, Sunil Kumar Gollapinni, Praveen Kumar Palisetti
  • Patent number: 11874791
    Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 16, 2024
    Assignee: Analog Devices, Inc.
    Inventors: Martin Kessler, Miguel A. Chavez, Lewis F. Lahr, William Hooper, Robert Adams, Peter Sealey
  • Patent number: 11874787
    Abstract: Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: January 16, 2024
    Assignee: Intel Corporation
    Inventors: Amit K Srivastava, Majid Shushtarian, Anand K Enamandram, Jared W Havican, Jeffrey A Pihlman, Michael J Karas, Ramamurthy Krithivas, Christine Watnik
  • Patent number: 11868785
    Abstract: Aspects of the disclosure provide a method and an apparatus for information processing. For example, the apparatus includes a storage medium, processing circuitry and network interface circuitry. The storage medium stores a first application program, and other application programs that are downloaded via the network interface circuitry. The processing circuitry executes the first application program in an operating system to provide a running environment. Further, the processing circuitry executes a second application program in the running environment to start a logic process and a first view process corresponding to a first view page of the second application program. The logic process and the first view process respectively interface with the running environment. The logic process generates initial first page data, and the initial first page data is transferred from the logic process to the first view process. The first view page is rendered in the first view process.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 9, 2024
    Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
    Inventors: Hao Hu, Haojun Hu, Qingjie Lin
  • Patent number: 11863561
    Abstract: The present embodiments relate to edge attestation of a host node to access a cloud infrastructure environment. A set of authentication data can be obtained from a console for authorization of the host node. The set of authentication data can include a first endorsement key and an authentication policy identifying characteristics of the host node. The host node can send a request for a network address to connect to the cloud infrastructure environment. The host node can generate a second endorsement key and authentication data that can be verified as corresponding to the set of authentication data received from the console. Responsive to validating the second endorsement key and the received host node authentication data, the network address can be provided to the host node that can be used to connect to the cloud infrastructure environment using the network address.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: January 2, 2024
    Assignee: Oracle International Corporation
    Inventor: Brian Spencer Payne
  • Patent number: 11842194
    Abstract: Systems and methods for illumination power, management and control can include lighting fixtures, lighting controllers, databases, and gateways. The lighting controllers can power the lighting fixtures, control the lighting fixtures, and store fixture state data and controller state data. The lighting controllers can be connected to building mains power (e.g., 240 VAC) and provide DC power to the lighting fixtures. The lighting controllers can read state data from and control the fixtures via a digital interface. The Database server can store user profiles, site profiles, fixture property data, and controller property data. The gateway can read and modify the state data stored by the lighting controllers, and can query the database server for the property data. The gateway can also provide a user interface through which users, based on authorization, can read and write the state data (e.g., fixture on/off) and the property data.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 12, 2023
    Assignee: NICOR, INC.
    Inventors: David Brown, Lucas Jackson
  • Patent number: 11841817
    Abstract: Methods and systems for facilitating an equitable bandwidth distribution across downstream devices in asymmetrical switch topologies, and in particular asymmetrical PCIe switch topologies. The equitable distribution of bandwidth is achieved in asymmetrical topologies using virtual switch partitioning. An upstream switch that is connected to the root complex via an upstream port and that receives bandwidth B from the upstream port, is virtualized into two or more virtual switches. Each virtual switch equally shares the bandwidth. Each virtual switch is allocated to downstream devices that are connected to the upstream switch as well as to one or more downstream switches that are connected to the upstream switch. Each downstream switch may be connected to one or more additional downstream devices.
    Type: Grant
    Filed: November 30, 2022
    Date of Patent: December 12, 2023
    Assignee: Google LLC
    Inventors: Pankaj Makhija, Nishant Patil
  • Patent number: 11842052
    Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.
    Type: Grant
    Filed: August 12, 2021
    Date of Patent: December 12, 2023
    Inventors: Wentao Wu, Sompong Paul Olarig
  • Patent number: 11836500
    Abstract: A method may include during a Pre-Extensible Firmware Interface Initialization phase of a BIOS, receiving a mailbox command from a management controller of an information handling system, the mailbox command including information regarding a driver image stored in computer-readable media associated with the BIOS, the information including uniquely-identifying information for the driver image. The method may also include, during a Driver Execution Environment phase of the BIOS, locating the driver image stored in the computer-readable media, verifying the driver image based on the information from the mailbox command, extracting the driver image from the computer-readable media in response to verifying the driver image, and causing a driver stored within the driver image to load and execute during BIOS execution.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: December 5, 2023
    Assignee: Dell Products L.P.
    Inventors: Shekar Babu Suryanarayana, Ibrahim Sayyed, Jagadish Babu Jonnada
  • Patent number: 11836501
    Abstract: A new approach is proposed to support hardware-based PCIe link up based on post silicon characterization of an electronic device. A non-volatile storage medium of a bootup unit on the electronic device maintains an initialization sequence for the physical layer of a PCIe link, and a non-volatile storage medium allows flexible programming. During operation, the bootup unit reads from the non-volatile storage medium instructions to program/override one or more PCIe physical layer settings and controller registers for the PCIe link based on the post silicon characterization of the electronic device. The bootup unit is limited to access and override only to the one or more physical layer settings and controller registers of the PCIe link. The entire process of reading the initialization sequence and programming the one or more PCIe physical layer settings and the controller registers happens within time limit constraints of the PCIe specification for latency reduction.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: December 5, 2023
    Assignee: Marvell Asia Pte Ltd
    Inventors: Ramacharan Sundararaman, Nithyananda Miyar
  • Patent number: 11836101
    Abstract: A system can include a host device that includes a downstream port and an endpoint device that includes an upstream port. A bidirectional multilane link can interconnect the downstream port and the upstream port. The downstream port can send a request to the upstream port across the bidirectional multilane link to change a number of active lanes in a first direction on the bidirectional multilane link, the request comprising an indication of a desired link width, receive an acknowledgment from the upstream port to change the number of active lanes on the bidirectional multilane link to the desired link width in the first direction, configure the bidirectional multilane link to operate using the desired link width, and send or receiving data to the upstream port using the desired link width. The change in link width can be asymmetrical (i.e., the upstream link width is different from the downstream link width).
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: December 5, 2023
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 11829778
    Abstract: Embodiments herein disclose a method for enhancing a performance of an electronic device. The method includes detecting a plurality of hardware features of the electronic device. Further, the method includes learning a usage pattern of each of the hardware features of the electronic device over a period of time using a machine learning model. Further, the method includes predicting at least one of a remaining usage time of a battery of the electronic device and at least one application to be launched by a user of the electronic device based on the usage pattern of each of the hardware features. Further, the method includes enhancing the performance of the electronic device based on at least one of the predicted remaining usage time of the battery and the at least one predicted application to be launched by the user.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: November 28, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Saurabh Pareek, Pioush Kumar, Ved Gangwar, Gaurav Yadav
  • Patent number: 11809340
    Abstract: A memory card includes first and second interface units connected to a system host, a memory unit, and an additional information registration unit. The memory unit includes a first identifier storage unit that stores an identifier of the memory unit, a flash memory, and a memory controller that controls the first identifier storage unit and the flash memory via the first interface unit. The additional information registration unit includes a second identifier storage unit that stores an identifier same as the identifier of the memory unit, and an additional information notification unit that notifies the system host of the identifier in the second identifier storage unit and additional information via the second interface unit. When the memory card is connected to the system host, the memory unit and the additional information registration unit are associated with each other by the identifiers stored in the first and second identifier storage units.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: November 7, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideaki Yamashita, Takeshi Ootsuka
  • Patent number: 11809875
    Abstract: A basic input/output system (BIOS) may load an embedded operating system (EOS), and the light-weight EOS may operate as a single captive portal for all pre-boot operations. With a single captive portal, the EOS may provide a multi-task environment to facilitate quicker execution of multiple pre-boot tasks within a single environment to reduce a number of reboots. In some embodiments, power consumption by performing the tasks within the EOS may be reduced by executing operations using a low-power core of an information handling system, such as a “little” core of a system on chip (SoC) having multiple “big” and “little” cores or a hybrid core of an information handling system. More generically, the EOS may execute on one or both of a first processor core and second processor core of an information handling system, in which the first and second processor cores are configured differently.
    Type: Grant
    Filed: October 7, 2021
    Date of Patent: November 7, 2023
    Assignee: Dell Products L.P.
    Inventors: Shekar Babu Suryanarayana, Sumanth Vidyadhara
  • Patent number: 11797334
    Abstract: A method and apparatus for BMC-parameter configuring and taking-effect, a device and a medium.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: October 24, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventor: Zhili Hou
  • Patent number: 11789887
    Abstract: The invention relates to a method for detecting the position of a bus subscriber (2, 2a, 2b, 2n) of a bus system, in which a control device (1) and several bus subscribers (2, 2a, 2b, 2n) are provided. The bus subscribers (2, 2a, 2b, 2n) are respectively in a position (P1, P2, Pn) to be detected and are connected to the control device (1) via at least one line, the line to the respective bus subscriber (2, 2a, 2b, 2n) having a definable line length (L1, L2, Ln), and the position of a bus subscriber (2, 2a, 2b, 2n) is then detected. The control device (1) emits a signal by means of an oscillator (3) via the line to the respective bus subscriber (2, 2a, 2b, 2n) and the bus subscriber (2, 2a, 2b, 2n) responds. The frequency of the oscillator (3) is determined and a ratio of frequency and line length (L1, L2, Ln) is used to detect the position.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: October 17, 2023
    Inventor: Peter Sättele
  • Patent number: 11789888
    Abstract: The invention relates to a method for detecting the position of a bus subscriber (2, 2a, 2b, 2n) of a bus system, in which a control device (1) and several bus subscribers (2, 2a, 2b, 2n) are provided. The bus subscribers (2, 2a, 2b, 2n) are respectively in a position (P1, P2, Pn) to be detected and are connected to the control device (1) via at least one line, the line to the respective bus subscriber (2, 2a, 2b, 2n) having a definable line length (L1, L2, Ln), and the position of a bus subscriber (2, 2a, 2b, 2n) is then detected in that the control device (1) sends a signal via the line to the respective bus subscriber (2, 2a, 2b, 2n) within a measurement cycle and the bus subscriber (2, 2a, 2b, 2n) responds. The measurement cycle duration is determined and a ratio of measurement cycle duration and line length (L1, L2, Ln) is used to detect the position.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 17, 2023
    Inventor: Peter Sättele