Patents Examined by Paul R. Myers
  • Patent number: 10838473
    Abstract: A method for protecting a computer system is performed by a smart connector is described. The smart connector tests an Internet connection provided by an Internet hub. The connector reboots the Internet hub if the testing detects a problem in the Internet connection. Then, the connector tests the Internet connection after rebooting the Internet hub. If the problem persists after rebooting the Internet hub, the connector sends a hub problem notification. The components of the smart connector are also described.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventor: R. Kent Koeninger
  • Patent number: 10838449
    Abstract: Automatic detection of clock grid misalignments and automatic realignment including loading a test pattern into a first storage element on a first clock grid on a circuit; scanning the test pattern from the first storage element on the first clock grid to a second storage element on a second clock grid on the circuit; reading the scanned test pattern from the second storage element on the second clock grid; evaluating the scanned test pattern for errors; and in response to detecting an error in the scanned test pattern, triggering an alignment of the first clock grid and the second clock grid.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: November 17, 2020
    Assignee: International Business Machines Corporation
    Inventors: Benedikt Geukes, Matteo Michel, Manfred Walz
  • Patent number: 10831483
    Abstract: An apparatus to facilitate doorbell notifications is disclosed. The apparatus includes memory-mapped I/O (MMIO) base address registers including a physical function (PF) and plurality of virtual functions (VF), wherein each function's base address register comprises a plurality of doorbell pages and doorbell hardware including doorbell registers, each having an assignable function identifier (ID) and offset, and comprising a plurality of doorbells to activate a doorbell notification in response to receiving a doorbell trigger from an associated doorbell page set upon detection of an access request.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Intel Corporation
    Inventors: Bryan R. White, Ankur N. Shah, Altug Koker, David Puffer, Aditya Navale
  • Patent number: 10831691
    Abstract: The present disclosure relates to a method for implementing processing elements in a chip card such that the processing elements can communicate data between each other in order to perform a computation task, wherein the data communication requires each processing element to have a respective number of connections to other processing elements. The method comprises: providing a complete graph with an even number of nodes that is higher than the maximum of the numbers of connections by one or two. If the number of processing elements is higher that the number of nodes of the graph, the graph may be duplicated and the duplicated graphs may be combined into a combined graph. A methodology for placing and connecting the processing elements may be determined in accordance with the structure of nodes of a resulting graph, the resulting graph being the complete graph or the combined graph.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Martino Dazzi, Pier Andrea Francese, Abu Sebastian, Riduan Khaddam-Aljameh, Evangelos Stavros Eleftheriou
  • Patent number: 10824427
    Abstract: A system and apparatus comprise at least one power supply connected to a terminal bloc, an I/O system configured to receive instructions provided to the control system, a control block connected to the I/O system wherein the instructions provided to the I/O system are converted to a serial output; and a puck connected to the serial output and configured to receive power from the terminal block, to process the serial output, and to output a current.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: November 3, 2020
    Assignee: NICOR, INC.
    Inventors: David Brown, Trevor Shaw, Jorge Alfredo Gomez Martinez
  • Patent number: 10802566
    Abstract: A two-part interface PHY configuration includes a low-voltage PHY portion configured for instantiation on an SoC device fabricated using a cutting-edge technology node, and a high-voltage PHY portion configured for instantiation on a power management device (PMD) fabricated using a high-voltage technology node. The low-voltage PHY portion includes interface control and low-voltage I/O circuitry configured to transfer outgoing 3.3V data signals to the high-voltage PHY portion at low voltage levels, and the high-voltage PHY portion includes a driver circuit that retransmits the low-voltage data signals onto a bus at the required 3.3V level. Incoming 3.3V data signals pass through an attenuator circuit before being processed using a receiver circuit provided on the low-voltage PHY portion. In USB applications, outgoing USB High Speed data signals are generated by a driver circuit provided on a low-voltage USB PHY portion.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Synopsys, Inc.
    Inventors: Andrew Chung Chun Lam, Davit Petrosyan, Dino A. Toffolon, Morten Christiansen
  • Patent number: 10803163
    Abstract: To ensure a simple and secure verification of a device, in particular of a safety controller, a method of verifying a configuration of a device, in particular of a safety controller, is provided, said method comprising the steps of subdividing the configuration of the device into at least two part configurations that are validated, of allocating the part configurations to at least one part configuration sequence in which a dependence on a verification of the part configurations on one another is predefined, of determining parameters of each part configuration, with the parameters being used for verifying the respective part configurations, of calculating a single checksum that reproduces the verification of the part configurations, with the single checksum of a preceding part configuration being recalculated in the verification of a part configuration following in the part configuration sequence and with the verification of the preceding part configuration being confirmed on an agreement of the single checksu
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: October 13, 2020
    Assignee: SICK AG
    Inventors: Harald Fecher, Jörg Moddemann, Martin Wehrle
  • Patent number: 10802573
    Abstract: A power management system and a power management method are provided. The power management system includes a host manager and at least one server. The server communicates with the host manager. The server includes at least one processor, at least one voltage regulator, and a voltage regulator controller. The voltage regulator provides an actual power to the corresponding processor. The voltage regulator controller adjusts the actual power provided by the voltage regulator. The host manager controls the voltage regulator controller in the server and uses the voltage regulator controller to adjust the actual power provided by the voltage regulator for managing a power of the processor.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: October 13, 2020
    Assignee: Wiwynn Corporation
    Inventors: Kui-Yeh Chen, Yi-Chen Luo, Chih-Yuan Hsu, Wei-Yu Chiang, Heng-I Chi
  • Patent number: 10795422
    Abstract: A method and apparatus for mission critical standby of a portable communication device are disclosed. A portable communication device may include a primary processor for a first operating platform, a secondary processor for a second operating platform and communicatively coupled to the primary processor, and a power state manager that may have a first mode and a second mode. The power state manager may be configured to determine whether the primary processor is in a powered off state and sequence supply of power to the secondary processor. The first mode may allow the primary processor to monitor a power state of the secondary processor based on a determination that the primary processor is not in the powered off state and the second mode may enable the power state manager to monitor the power state based on a determination that the primary processor is in the powered off state.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 6, 2020
    Assignee: Motorola Solutions, Inc.
    Inventors: Daniel Grobe Sachs, Graeme Johnson, Stephen C. Glass, Peter J. Bartels, Javier Alfaro, Carlos Camps
  • Patent number: 10795842
    Abstract: Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a data system is provided. The data system includes a first assembly comprising a plurality of modular storage bays populated with one or more graphics processing modules each including a graphics processing unit (GPU), wherein the plurality of modular storage bays each comprise a bay connector that includes a bay Peripheral Component Interconnect Express (PCIe) connection. The first assembly further comprises PCIe switch circuitry configured to communicatively couple the bay PCIe connections to a PCIe fabric over one or more external PCIe links.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: October 6, 2020
    Assignee: Liqid Inc.
    Inventors: Jason Breakstone, Christopher R. Long, German Kazakov, James Scott Cannata
  • Patent number: 10795841
    Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Venkatraman Iyer, Darren Jue, Sitaraman Iyer
  • Patent number: 10789180
    Abstract: A serial peripheral interface (SPI)-based data transmission method, including sending, by a first device, a first query request to a second device through a universal asynchronous receiver/transmitter (UART) interface, where the first query request queries the second device for an SPI mode supported by the second device, sending, by the first device, in response to the first device determining, according to a first query response returned by the second device, that the second device supports an SPI master mode, an SPI connection establishment request to the second device, where the SPI connection establishment request causes the second device to initiate establishment of an SPI connection to the first device, and performing, by the first device, through the SPI, and after the first device establishes the SPI connection to the second device, at least one of receiving data sent by the second device, or sending data to the second device.
    Type: Grant
    Filed: January 16, 2017
    Date of Patent: September 29, 2020
    Inventor: Shaohua Zhong
  • Patent number: 10789191
    Abstract: A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be configured to register I/O interrupts and queue I/O operations. When no application code is executing, the OS may be configured to call appropriate interrupt handlers. As result, the OS may maintain the real-time execution that may be required of applications on an embedded system while providing the flexibility and scalability offered by an operating system.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: September 29, 2020
    Assignee: Andium Inc.
    Inventors: Jory Schwach, Brian Bosak
  • Patent number: 10776026
    Abstract: Techniques for performing compression operations on persistently-stored data blocks during read/write commands. A method embodiment performs in-line data compression operations over data blocks referenced by a caller. The in-line data compression operations are performed during execution of a storage input-output (I/O) command, between the event of receipt of the storage I/O command and the event of returning status of the storage I/O command. The storage I/O operation is associated with at least one data group comprising one or more data blocks that are identified by the caller. Upon receipt of the storage I/O command, one or more compression rules are applied to the data blocks to determine one or more compression parameters, which compression parameters are used to form specific compression operations that are performed over at least a portion of the data group. The status pertaining to the execution of the storage I/O operation is returned to the caller.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 15, 2020
    Assignee: Nutanix, Inc.
    Inventors: ChernYih Cheah, Kiran Tatiparthi, Manosiz Bhattacharyya, Varun Kumar Arora
  • Patent number: 10754997
    Abstract: A controller area network (CAN) controller and transceiver device implementing an output CAN network as a mirror of an adjacent connected input CAN network, the output CAN network and the input can network both comprising at least first data wires. The system includes a first diode device interposing the input and output CAN networks such that a signal on the first data wire of the input CAN network can propagate to the first data wire of the output CAN network but not vice versa.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: August 25, 2020
    Assignee: The University of Tulsa
    Inventors: Jeremy Daily, Hayden Allen
  • Patent number: 10747282
    Abstract: An electronic device includes a power management circuit generating output for a plurality of voltage monitors that each detect whether voltages received from a test apparatus are at least a different minimum threshold. The power management circuit also generates a test enable signal indicative of whether the test apparatus is supplying the minimum required voltages to the electronic device. A control circuit receives the output for the plurality of voltage monitors and the test enable signal and generates at least one control signal as a function of the output for the plurality of voltage monitors and the test enable signal. An output circuit receives the at least one control signal and generates an interface control signal that selectively enables or disables interface with analog intellectual property packages within the electronic device, in response to the at least one control signal.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: August 18, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Srinivas Dhulipalla, Sandip Atal
  • Patent number: 10749706
    Abstract: The present invention relates to an integrated circuit device for controlling LIN slave nodes based on a control signal transmitted by a LIN master control device. The IC device comprises a slave node circuit for processing the control signal when received in the form of a LIN message frame via a first data line terminal. The IC device also comprises a master node circuit for processing further control signals to be transmitted in the form of LIN message frames via a second data line terminal to the LIN slave nodes. The IC device also comprises a processing unit for controlling the LIN slave nodes based on the control signal by composing the further control signals.
    Type: Grant
    Filed: June 14, 2017
    Date of Patent: August 18, 2020
    Inventors: Michael Bender, Philip Mckenna, Thomas Freitag
  • Patent number: 10739835
    Abstract: In one example in accordance with the present disclosure a method of is described. According to the method, usage data for an electronic device is obtained. An activity phase from a plurality of activity phases for the electronic device is selected based on the usage data. An activity phase has a corresponding timeout period and is defined by an inter-arrival threshold. The electronic device is instructed to enter a low power mode after being inactive for a time period at least as great as the timeout period corresponding to a selected activity phase.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: August 11, 2020
    Assignees: Hewlett-Packard Development Company, L.P., Purdue Research Foundation
    Inventors: Hernan Ildefonso Gutierrez-Vazquez, Mark J. Wibbels, Jan Allebach, Perry Victor Lea, Ganesh Prahlad Rao Gingade, Wenyi Chen, Yung-Hsiang Lu
  • Patent number: 10740275
    Abstract: Logic circuitry packages for association with replaceable print apparatus components are disclosed herein. An example logic circuitry package includes logic and a serial data bus interface. The serial data bus interface is to interface with a serial data bus of a print apparatus, and the logic is, in response to a first command sent to the logic circuitry package via the serial data bus connected to the serial data bus interface, to generate a low voltage condition on the serial data bus and to monitor a duration of a time period.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: August 11, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen D. Panshin, Scott A. Linn
  • Patent number: 10733136
    Abstract: Semiconductor substrate sections joined by an integral flexible cable are utilized to form a device comprising a connector. The connector can be surface mounted on through-holes and soldered for enhanced robustness.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventor: Khoon Guan Tee