Abstract: A system can include a host device that includes a downstream port and an endpoint device that includes an upstream port. A bidirectional multilane link can interconnect the downstream port and the upstream port. The downstream port can send a request to the upstream port across the bidirectional multilane link to change a number of active lanes in a first direction on the bidirectional multilane link, the request comprising an indication of a desired link width, receive an acknowledgment from the upstream port to change the number of active lanes on the bidirectional multilane link to the desired link width in the first direction, configure the bidirectional multilane link to operate using the desired link width, and send or receiving data to the upstream port using the desired link width. The change in link width can be asymmetrical (i.e., the upstream link width is different from the downstream link width).

Abstract: Embodiments herein disclose a method for enhancing a performance of an electronic device. The method includes detecting a plurality of hardware features of the electronic device. Further, the method includes learning a usage pattern of each of the hardware features of the electronic device over a period of time using a machine learning model. Further, the method includes predicting at least one of a remaining usage time of a battery of the electronic device and at least one application to be launched by a user of the electronic device based on the usage pattern of each of the hardware features. Further, the method includes enhancing the performance of the electronic device based on at least one of the predicted remaining usage time of the battery and the at least one predicted application to be launched by the user.

Abstract: A memory card includes first and second interface units connected to a system host, a memory unit, and an additional information registration unit. The memory unit includes a first identifier storage unit that stores an identifier of the memory unit, a flash memory, and a memory controller that controls the first identifier storage unit and the flash memory via the first interface unit. The additional information registration unit includes a second identifier storage unit that stores an identifier same as the identifier of the memory unit, and an additional information notification unit that notifies the system host of the identifier in the second identifier storage unit and additional information via the second interface unit. When the memory card is connected to the system host, the memory unit and the additional information registration unit are associated with each other by the identifiers stored in the first and second identifier storage units.

Abstract: A basic input/output system (BIOS) may load an embedded operating system (EOS), and the light-weight EOS may operate as a single captive portal for all pre-boot operations. With a single captive portal, the EOS may provide a multi-task environment to facilitate quicker execution of multiple pre-boot tasks within a single environment to reduce a number of reboots. In some embodiments, power consumption by performing the tasks within the EOS may be reduced by executing operations using a low-power core of an information handling system, such as a “little” core of a system on chip (SoC) having multiple “big” and “little” cores or a hybrid core of an information handling system. More generically, the EOS may execute on one or both of a first processor core and second processor core of an information handling system, in which the first and second processor cores are configured differently.

Abstract: A method and apparatus for BMC-parameter configuring and taking-effect, a device and a medium.

Abstract: The invention relates to a method for detecting the position of a bus subscriber (2, 2a, 2b, 2n) of a bus system, in which a control device (1) and several bus subscribers (2, 2a, 2b, 2n) are provided. The bus subscribers (2, 2a, 2b, 2n) are respectively in a position (P1, P2, Pn) to be detected and are connected to the control device (1) via at least one line, the line to the respective bus subscriber (2, 2a, 2b, 2n) having a definable line length (L1, L2, Ln), and the position of a bus subscriber (2, 2a, 2b, 2n) is then detected. The control device (1) emits a signal by means of an oscillator (3) via the line to the respective bus subscriber (2, 2a, 2b, 2n) and the bus subscriber (2, 2a, 2b, 2n) responds. The frequency of the oscillator (3) is determined and a ratio of frequency and line length (L1, L2, Ln) is used to detect the position.

Abstract: The invention relates to a method for detecting the position of a bus subscriber (2, 2a, 2b, 2n) of a bus system, in which a control device (1) and several bus subscribers (2, 2a, 2b, 2n) are provided. The bus subscribers (2, 2a, 2b, 2n) are respectively in a position (P1, P2, Pn) to be detected and are connected to the control device (1) via at least one line, the line to the respective bus subscriber (2, 2a, 2b, 2n) having a definable line length (L1, L2, Ln), and the position of a bus subscriber (2, 2a, 2b, 2n) is then detected in that the control device (1) sends a signal via the line to the respective bus subscriber (2, 2a, 2b, 2n) within a measurement cycle and the bus subscriber (2, 2a, 2b, 2n) responds. The measurement cycle duration is determined and a ratio of measurement cycle duration and line length (L1, L2, Ln) is used to detect the position.

Abstract: Methods, systems, and apparatuses for configuring a device for a specific task or set of tasks thereby allowing the device to be used for more than one task or set of tasks while also enabling fine-grain control over how the device may be used. A device's file system can operate with a particular file system based on the task(s) that the device will perform. Further, the device can physically configure itself based on the task(s) that the device will perform.

Abstract: A method includes determining a traffic pattern of access requests within a queue or a system, or both and dynamically adjusting, within a particular range, a queue depth of the queue based on the determined traffic pattern of access requests to balance bandwidth and latency associated with executing the access requests.

Abstract: A transaction ordering system is configured to order various transactions initiated by one device for execution with another device. The transaction ordering system includes ordering circuitry that is configured to generate two pointer values such that one pointer value corresponds to a transaction identifier (ID) of a transaction that is to be processed, and another pointer value corresponds to a transaction ID of a latest initiated transaction. Based on the two pointer values, the ordering circuitry orders the transactions such that if a first transaction is initiated before a second transaction, a set of data packets associated with the first transaction is transmitted to the transaction initiating device before a set of data packets associated with the second transaction is transmitted.

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.

Abstract: The techniques disclosed herein improve existing systems by providing a system that receives a settings profile associated with a first application. The settings profile is stored. When it is determined that a second application has unconfigured settings, the stored settings profile is accessed and based on the stored settings profile, the unconfigured settings are automatically configured.

Abstract: Systems, apparatuses, and methods for performing geometry work in parallel on multiple chiplets are disclosed. A system includes a chiplet processor with multiple chiplets for performing graphics work in parallel. Instead of having a central distributor to distribute work to the individual chiplets, each chiplet determines on its own the work to be performed. For example, during a draw call, each chiplet calculates which portions to fetch and process of one or more index buffer(s) corresponding to one or more graphics object(s) of the draw call. Once the portions are calculated, each chiplet fetches the corresponding indices and processes the indices. The chiplets perform these tasks in parallel and independently of each other. When the index buffer(s) are processed, one or more subsequent step(s) in the graphics rendering process are performed in parallel by the chiplets.

Abstract: A communication control device according to an embodiment includes one or more hardware processors functioning as a transmission control unit and a communication unit. The transmission control unit performs control of transmission of messages by opening and closing a gate based on transmission permission information. The transmission permission information is generated based on gate control information including a plurality of entries for determining whether to open a plurality of gates corresponding to a plurality of queues. The transmission permission information indicates an amount of transmittable messages in a period corresponding to one or more continuous entries. The communication unit transmits and receives messages in accordance with the control of the transmission control unit.

Abstract: Methods and apparatus for arbitration and access to hardware request ring structures in a concurrent environment. A request ring mechanism is provided including an arbiter, ring overflow guard, request ring, and request ring metadata, each of which is implemented in shared virtual memory (SVM) on a computing platform including a multi-core processor coupled to an offload device having one or more SVM-capable accelerators. Worker threads request to access the request ring to provide job descriptors to be processed by the accelerator(s). A lockless arbiter returns either an index of a slot in which to write a descriptor or information indicating the ring is full to each worker thread. The scheme enables worker threads to write descriptors to slots in the request ring corresponding to the returned indexes without contention from other worker threads. The ring overflow guard prevents valid descriptors from being overwritten before they are taken off the ring by the accelerator(s).

Abstract: The present disclosure provides a hot-plugging control method, device, and retimer. The hot-plugging control method includes: receiving data from a pluggable device through a second end, sending the data to an RC through a first end; sending a detection signal to the second end to detect the connection status between the pluggable device and the second end; and stopping sending the data to the RC, and sending the first control signal to the RC, when it is detected that the pluggable device is hot-unplugged from the second end, so that the RC handles the abnormal state of the data not being sent according to the first control signal. The hot-plugging control method provided by the present disclosure does not require presence signals to implement hot-plugging of a pluggable device, and thus can avoid the problem that the device cannot implement hot-plugging without presence signals.

Abstract: An automation arbitration controller system is provided. The automation arbitration controller is configured to arbitrate a multiple of automation requests on a material handling vehicle, which includes a material handling vehicle controller. The automation arbitration controller can be connected to at least one automation controller via an automation communication bus. The automation controller can be configured to send one or more automation requests. The automation arbitration controller can also be connected to a material handling vehicle controller via a vehicle communication bus. The material handling vehicle controller can be configured to send one or more automation requests.

Abstract: Techniques for performing compression operations on persistently-stored data blocks during read/write commands. A method embodiment performs in-line data compression operations over data blocks referenced by a caller. The in-line data compression operations are performed during execution of a storage input-output (I/O) command, between the event of receipt of the storage I/O command and the event of returning status of the storage I/O command. The storage I/O operation is associated with at least one data group comprising one or more data blocks that are identified by the caller. Upon receipt of the storage I/O command, one or more compression rules are applied to the data blocks to determine one or more compression parameters, which compression parameters are used to form specific compression operations that are performed over at least a portion of the data group. The status pertaining to the execution of the storage I/O operation is returned to the caller.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: register a subroutine configured to store multiple addresses of a volatile memory medium VMM of an information handling system (IHS); for each IHS initialization executable/OS executable pair of multiple IHS initialization executable/OS executable pairs: retrieve, from a first non-volatile memory medium (NVMM), an IHS initialization executable of the IHS initialization executable/OS executable pair; copy, by the IHS initialization executable, an OS executable of the IHS initialization executable/OS executable pair from the first NVMM to the VMM; call, by the IHS initialization executable, the subroutine; store, by the subroutine, an address associated with the OS executable via a data structure stored by the VMM; and copy, by a first OS executable, the OS executable from the VMM to a second NVMM based at least on the address associated with the OS executable.

Abstract: Apparatus comprises a data memory to store lock data for each of a set of processing resources, the lock data representing lock status data and tag data indicating a resource type selected from a plurality of resource types; and a processing element to execute an atomic operation with respect to the lock data for a given processing resource, the atomic operation comprising at least: a detection of whether the given processing resource is of a required resource type; a detection from the lock status data whether the given processing resource is currently unlocked; and when the given processing resource is detected to be currently unlocked and of the required resource type, performance of a predetermined action with respect to one or both of the lock status data and the tag data.