Abstract: Disclosed are a high-speed real-time bus system and a data processing method thereof. Each node device forms an annularly connected topological structure by means of a high-speed real-time bus; a master node device respectively sends a bus clock signal and a data signal to a slave node device of the next grade of the master node device in the topological structure by means of a clock channel and a data channel; each slave node device receives the bus clock signal and the data signal sent from the respective node device of the previous grade, performs data processing according to the bus clock signal and the data signal so as to update the data signal and sends the bus clock signal and the updated data signal to the respective node device of the next grade.

Abstract: Disclosed herein are system, computer-readable storage medium, and method embodiments of machine-learning (ML)-based static verification for derived hardware-design elements. A system including at least one processor may be configured to extract a feature set from a hardware description and evaluate a similarity index of a first hardware element with respect to a second hardware element, using an ML process based on the feature set, wherein the first hardware element is described in the hardware description. The at least one processor may be further configured to update one or more parameters corresponding to a static verification of the hardware description while the static verification is being performed, by providing at least one test attribute, corresponding to the second hardware element, applicable to the first hardware element, in response to determining that the similarity index is within a specified range, and additionally output a first result of the static verification.

Abstract: The present disclosure relates to a communication system for serial communication. The communication system may include a master communication device; and at least one slave communication device comprising a unique identifier, wherein the master communication device is connected to the at least one slave communication device via a signal line configured for communications, wherein the master communication device is configured to read at least a part of the unique identifier via the signal line, and assign an address to the at least one slave communication device based at least in part on the unique identifier, and transmit the address to the at least one slave communication device via the signal line.

Abstract: A first mode setting signal is received from a host system. The first mode setting signal indicates a first mode. A memory component is memory component to the first mode based on the first mode setting signal. In the first mode, memory cells of the memory component are exposed to the host system. A second mode setting signal is received from the host system. The second mode setting signal indicates a second mode. The memory component is set to the second mode based on the second mode setting signal. In the second mode, a machine learning operation component of the memory component is exposed to the host system.

Abstract: A device and a method for a transmitter/receiver device of a bus system are provided. The device has a measuring unit for measuring a minimum recessive bit time that occurs during an operation of the bus system in a message received by the device from a bus of the bus system, a voltage state of the message having been actively driven by a transmitter/receiver device of one of at least two user stations of the bus system; a calculation unit for calculating a power-on period on the basis of the minimum recessive bit time supplied by the measuring unit, the power-on period being a time period for which an oscillation reduction unit is to be switched on, which is used for reducing oscillations on the bus that occur after a transition between different voltage states of a bus signal transmitted on the bus.

Abstract: First and second clock signals are generated based on signal transitions within first and second streams of symbols, respectively, received within an integrated circuit component, the first and second clock signals having a time-varying phase offset with respect to one another. A first control circuit, operating in a first timing domain established by the first clock signal, generates first control information based on the first stream of symbols and forwards the first control information, via a domain crossing circuit that bridges the time-varying phase offset, to a second control circuit operating in a second timing domain. The second control circuit generates a third stream of symbols based on the first control information and on the second stream of symbols, and a transmit circuit outputs the third stream of symbols from the integrated circuit component synchronously with respect to the second clock signal.

Abstract: A method to generate configuration data to enable and/or to enhance real-time communication in a cyber-physical system or in a cyber-physical system of systems. The system includes components connected to each other by a communication infrastructure. The components each execute at least one application, which applications exchange information with at least one application being executed on another component. The components are configured to send and/or receive said information according to configuration data: The first configuration data for two or more of the components, on each of which at least one application is executed, is generated by execution of a publish-subscribe protocol, which is executed by two or more of the components, for which the first configuration data are provided.

Abstract: Disclosed are a module assembly including: a code transmission module including a functional unit including a PnP code transmission unit transmitting a PnP code to a PnP module; and at least one PnP module driven by receiving the PnP code from the code transmission module, in which the PnP code is a code to drive the PnP module including a different functional unit from the code transmission module, and a plug and play system.

Abstract: Single-counter, multi-trigger systems and methods in communication systems consolidate tracking of multiple trigger events into a single counter in place of plural counters. The single counter may track multiple trigger events for a single triggered element. Likewise, the single counter may track trigger events for a plurality of triggered elements. By consolidating tracking of trigger events with reference to a single counter, the size of the circuit may be reduced and power savings may be achieved.

Abstract: A computing system is provided, including a processor and memory storing instructions that, when executed, cause the processor to store a firmware update patch in a runtime buffer included in the memory. The runtime buffer may be accessible by firmware and an operating system of the computing system. The processor may perform a first verification check on the firmware update patch. When the firmware update patch passes the first verification check, the processor may copy the firmware update patch to a system management random access memory (SMRAM) buffer included in the memory. The SMRAM buffer may be accessible by the firmware and inaccessible by the operating system. The processor may perform a second verification check on the copy of the firmware update patch. When the copy of the firmware update patch passes the second verification check, the processor may execute the copy of the firmware update patch.

Abstract: In an example, a logic circuitry package is configured to be addressable via a first address and at least one second address and comprises a first logic circuit. The first address may be an address for the first logic circuit, and the package may be configured such that, in response to a first command indicative of a first command time period sent to the first address, the package is accessible via at least one second address for a duration of the first command time period; and in response to a second command indicative of a second command time period sent to the first address, the first logic circuit is to, for a duration of the second command time period, disregard traffic sent to the first address.

Abstract: In order to manage power on a wearable computing device, a processor of the wearable computing device identifies one or more events. The processor determines a priority of each of the one or more events. Based on the priority of each of the one or more events, the processor determines whether to process the event. When the processor determines that the event is to be processed, the processor determines whether to defer processing of the event.

Abstract: A logic circuitry package for a replaceable print apparatus component comprises at least one logic circuit and an interface to communicate with a print apparatus logic circuit. The at least one logic circuit is configured to receive, via the interface, calibration parameters including an offset parameter and a sensor ID. The at least one logic circuit is configured to output, via the interface, a digital value corresponding to the sensor ID and offset based on the offset parameter.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: register a subroutine configured to store multiple network resource addresses via a volatile memory medium; for each information handling system (IHS) initialization executable of multiple IHS initialization executables: retrieve, from a non-volatile memory medium, the IHS initialization executable; execute the IHS initialization executable via an environment associated with IHS firmware; call, by the IHS initialization executable, the subroutine; and store, by the subroutine, a network resource address associated with an operating system (OS) executable via command line arguments, where the command line arguments are stored via a data structure in the volatile memory medium; and for each network resource address of the command line arguments: retrieve, based at least on the network resource address, an OS executable associated with the network resource address from another IHS via a network.

Abstract: In an embodiment, a power management system includes a detection unit configured to detect a power interruption to a power supply. The system further includes a communication interface configured to, in response to the detected power interruption, provide a message regarding the detected power interruption. In response to the detected power interruption, a computer network switch provides notifications to a plurality of servers connected to the switch to allow the plurality of servers to prepare for a loss in power.

Abstract: Groups of signal conductors within a configurable communication system are managed by respective, dedicated media controllers implement a configurable number of independent communication channels through coordinated action so that signal conductors need not be multiplexed to/from multiple controllers and no media controllers or input/output driver circuits therein need be disabled in any configuration.

Abstract: DMA architectures capable of performing multi-level multi-striding and determining multiple memory addresses in parallel are described. In one aspect, a DMA system includes one or more hardware DMA threads. Each DMA thread includes a request generator configured to generate, during each parallel memory address computation cycle, m memory addresses for a multi-dimensional tensor in parallel and, for each memory address, a respective request for a memory system to perform a memory operation. The request generator includes m memory address units that each include a step tracker configured to generate, for each dimension of the tensor, a respective step index value for the dimension and, based on the respective step index value, a respective stride offset value for the dimension. Each memory address unit includes a memory address computation element configured to generate a memory address for a tensor element and transmit the request to perform the memory operation.

Abstract: In some examples, a computing device may initiate a chat session with a software agent on a server. During the chat session, the software agent may ask questions and receive answers in response. The server may process logs sent from the computing device and a transcript of the chat session to identify tokens. A supervised learning model on the server may select a script based on the tokens and send the script to the computing device. The computing device may store the script in non-volatile memory and boot into a setup state of a basic input output system (BIOS) of the computing device. The BIOS may retrieve the script, convert BIOS procedure calls in the script into an action tree, and execute the actions in the action tree, causing a virtual mouse and/or virtual keyboard to provide input to the BIOS to modify the BIOS to address an issue.

Abstract: An example apparatus can include a host device and an apparatus including a memory device and a controller coupled to the memory device, wherein the host device is configured to send a command to read an image to configure the host to boot from the memory device to the controller and wherein a base address register is configured to receive the command, indicate the size of the image, and redirect the command to a first image in memory using a first register that indicates a size of the first image and a second register that indicates a location of the first image.

Abstract: A virtualized transaction terminal platform is provided. A transaction terminal is configured as a thin-client terminal. A virtualized transaction terminal (Virtual Machine (VM)) is instantiated remotely on a cloud or a server over a network connection. Peripherals connected to the thin-client terminal are mapped to virtual peripheral device drivers on the cloud or the server. Physical peripherals connected to the thin-client terminal are mapped inside the VM to the corresponding virtual peripheral device drivers. As transactions are initiated and physical peripherals are operated at the thin-client terminal, the transactions are processed by the VM and inputs/outputs from the physical peripherals are forwarded for processing by the corresponding virtual peripheral device drivers. A remote desktop (RD) agent on the thin-client terminal keeps states of the VM and virtual peripheral device drivers in synchronization with a peripheral display of the thin-client terminal.