Abstract: A system can include a memory device with an array of memory cells and a machine learning operation component. The machine learning operation component can perform a machine learning computation in association with the array of memory cells. The system can also include a processing device that is operatively coupled with the memory device to perform operations that include setting the memory device to a first mode based on a first mode setting signal received from a host system, where in the first mode, the processing device exposes the array of memory cells to the host system and routes input data from the host system to the array of memory cells. The operations can also include, setting the memory device to a second mode, where in the second mode, the processing device exposes the machine learning operation component to the host system.

Abstract: An apparatus comprises a processing device configured to generate connectivity information associated with at least one of a first device coupled to a first cable connector at a first end of a cable and a second device coupled to a second cable connector at a second end of the cable opposite the first end of the cable. The processing device is also configured to provision, via an integrated sideband interface of the cable, the generated connectivity information for display on at least one of a first cable display proximate the first cable connector at the first end of the cable and a second cable display proximate the second cable connector at the second end of the cable.

Abstract: Provided are embodiments for operating a high-speed deserializer. Embodiments can include receiving a clock slip signal to enable operation of the slip pulse generation circuit, and generating a slip pulse signal using the slip pulse-controlled clock generation circuit, wherein the slip pulse signal is programmable to slip one or more bits of a serial input data. Embodiments can also include generating a plurality of deserialization clocks for sampling the serial input data using the slip pulse-controlled clock generation circuit, wherein the plurality of deserialization clocks are generated simultaneously with each other, and providing the plurality of deserialization clocks to the deserializer to selectively sample the serial input data.

Abstract: Systems, apparatus and methods are provided for multi-drop multi-load NAND interface topology where a number of NAND flash devices share a common data bus with a NAND controller. A method for controlling on-die termination in a non-volatile storage device may comprise receiving a chip enable signal on a chip enable signal line from a controller, receiving an on-die termination (ODT) command on a data bus from the controller while the chip enable signal is on, decoding the on-die termination command and applying termination resistor (RTT) settings in the ODT command to a selected non-volatile storage unit at the non-volatile storage device to enable ODT for the selected non-volatile storage unit.

Abstract: Systems, apparatuses, and methods for saving power on a bus interface are described. A system includes a host, a device, and a repeater interposed between the host and the device. While the host and device are in a low-power state, the repeater monitors a first bus to determine if the device has woken up. When the repeater detects a remote wake-up event initiated by the device, the repeater generates an interrupt which is sent to the host. The host responds to the interrupt by initiating a resume wake-up event procedure that assumes the device is still asleep. In this way, the host is able to stay in the low-power state longer while also using a wake-up procedure that does not require the host to be aware of the existence of the repeater.

Abstract: The invention relates to a system for establishing a data connection between a master unit (M) and at least one device unit (D), wherein the master unit (M) is coupled to a primary coupler unit (Dprim) and the at least one device unit (D) is coupled to a secondary coupler unit (Dsec), in each case for electrical power transmission and for data transmission. The primary coupler unit (Dprim) and the secondary coupler unit (Dsec) can be coupled for data transmission. A control signal can be received and the system has three operating states that can be activated in dependence on the received control signal. When the first operating state is activated, there is a data connection according to the IO-Link standard between the master unit (M) and the device unit (D).

Abstract: A communication device that can prevent the transmission of a message from being continuously hindered over a long period of time, a communication system and a message arbitration method are provided. The communication device transmits and receives a message to and from another device connected to a common communication line which comprises a calculation unit that calculates as to a message to be transmitted a margin time before a time when a transmission of the message is completed; a transmission unit that transmits the message to which information related to the margin time calculated by the calculation unit is attached; and an arbitration unit that performs arbitration based on the information attached to the message when simultaneous message transmissions to the communication line occur, and as to multiple of messages simultaneously transmitted to the communication line, the arbitration unit performs arbitration in such a manner as to prioritize a message with a shorter margin time.

Abstract: Examples described herein relate to multiple processor nodes which are physically separate with interfaces to a common network interface. A local processor can run a timing recovery algorithm, and tune the master timer to align with the network domain to cause the master timer and network timing domains to be in the same domain. A common master timer can be used to align time stamps of independent processor nodes. A processor node can use the common master timer as a reference and the processor does not need to communicate with another processor to synchronize its timer.

Abstract: A method for execution by a low voltage drive circuit (LVDC) operably coupled to a bus includes, when activated, setting data reception for a control channel of a plurality of channels on the bus, where the control channel is a sinusoidal signal having a known frequency. The method further includes receiving the control channel and capturing a cycle of the control channel when the control channel is void of a data communication. The method further includes comparing the cycle of the control channel with a cycle of a first receive clock signal of the LVDC and when the cycle of a first receive clock signal compares unfavorably to the cycle of the control channel, adjusting phase and/or frequency of the cycle of the first receive clock signal to substantially match phase and/or frequency of the cycle of the control channel to produce an adjusted first receive clock signal.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more methods may: register a subroutine configured to store multiple network resource addresses via a volatile memory medium; for each information handling system (IHS) initialization executable of multiple IHS initialization executables: retrieve, from a non-volatile memory medium, the IHS initialization executable; execute the IHS initialization executable via an environment associated with IHS firmware; call, by the IHS initialization executable, the subroutine; and store, by the subroutine, a network resource address associated with an operating system (OS) executable via command line arguments, where the command line arguments are stored via a data structure in the volatile memory medium; and for each network resource address of the command line arguments: retrieve, based at least on the network resource address, an OS executable associated with the network resource address from another IHS via a network.

Abstract: Systems and methods are disclosed, including, in a storage system comprising control circuitry and a memory array having multiple groups of memory cells, storing a first physical-to-logical (P2L) data structure for a first physical area of a first group of memory cells in a second physical area of the first group of memory cells, such as when resuming operation from a low-power state, including an asynchronous power loss (APL). The first group of memory cells can include a super block of memory cells. A second P2L data structure for the second physical area of the first group of memory cells can be stored, such as in a metadata area of the second physical area and an address of the first P2L data structure can be stored in the second P2L data structure.

Abstract: A storage system is provided. The storage system includes a plurality of storage units, each having a controller and solid-state storage memory. The storage system further includes one or more first pathways that couple processing devices of a plurality of storage nodes and is configured to couple to a network external to the storage system and one or more second pathways that couple the plurality of storage nodes to the plurality of storage units, wherein the one or more second pathways enable multiprocessing applications.

Abstract: A system and apparatus comprise at least one power supply connected to a terminal bloc, an I/O system configured to receive instructions provided to the control system, a control block connected to the I/O system wherein the instructions provided to the I/O system are converted to a serial output; and a puck connected to the serial output and configured to receive power from the terminal block, to process the serial output, and to output a current.

Abstract: A system for managing a time reference includes a real-time clock, an interface, and a processor. The real-time clock store an RTC time. The interface is configured to receive a GPS time and a cellular time. The processor is configured to: indicate to start a time-speed adjustment loop; determine a true time based at least in part on the GPS time and the cellular time; determine an error between the true time and the RTC time; determine an RTC speed calibration adjustment based at least in part on the error; and adjust the real-time clock speed based at least in part on the RTC speed calibration adjustment.

Abstract: Systems and methods for illumination power, management and control can include lighting fixtures, lighting controllers, databases, and gateways. The lighting controllers can power the lighting fixtures, control the lighting fixtures, and store fixture state data and controller state data. The lighting controllers can be connected to building mains power (e.g., 240 VAC) and provide DC power to the lighting fixtures. The lighting controllers can read state data from and control the fixtures via a digital interface. The Database server can store user profiles, site profiles, fixture property data, and controller property data. The gateway can read and modify the state data stored by the lighting controllers, and can query the database server for the property data. The gateway can also provide a user interface through which users, based on authorization, can read and write the state data (e.g., fixture on/off) and the property data.

Abstract: In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.

Abstract: A Point-Of-Sale (POS) processing environment is encapsulated within a container running on a first Operating System (OS) of a transaction terminal. Peripheral drivers for connected peripherals run on a second and different OS of the transaction terminal. A platform processing environment runs the peripheral drivers on the second and different OS of the terminal. A socket interface is provided for communication between transaction applications of the POS processing environment with the peripheral drivers of the platform processing environment for purposes of allowing the transaction applications to control and access the connected peripherals during transactions performed at the transaction terminal via the socket interface.

Abstract: Disclosed herein is a method for designing a semiconductor device, the method including: assigning a plurality of wiring tracks including first and second tracks; connecting a first data I/O circuit to a first data node of a first circuit by a first signal bus arranged on the first wiring track; connecting a second data I/O circuit to a second data node of the first circuit by a second signal bus arranged on the second wiring track when a first design mode is selected; and connecting the first data I/O circuit to a second circuit by a second signal bus arranged on the second wiring track when a second design mode is selected.

Abstract: A new approach is proposed to support hardware-based PCIe link up based on post silicon characterization of an electronic device. A non-volatile storage medium of a bootup unit on the electronic device maintains an initialization sequence for the physical layer of a PCIe link, and a non-volatile storage medium allows flexible programming. During operation, the bootup unit reads from the non-volatile storage medium instructions to program/override one or more PCIe physical layer settings and controller registers for the PCIe link based on the post silicon characterization of the electronic device. The bootup unit is limited to access and override only to the one or more physical layer settings and controller registers of the PCIe link. The entire process of reading the initialization sequence and programming the one or more PCIe physical layer settings and the controller registers happens within time limit constraints of the PCIe specification for latency reduction.

Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.