Abstract: A docking station having adaptor function contains: an AC-DC conversion module, a charging module, a control module, and at least two interface modules. When an AC power source outputs AC power into the AC-DC conversion module, the AC-DC conversion module outputs two DC powers to the charging module and the control module according to the AC power. The control module is enabled to operate according to the first DC power. And, according to the second DC power, the control module controls the power charging module to charge each target end-user devices being connected to a corresponding interface module. When interface modules respectively connect to target end-user devices, the control module controls the signal transmission sequence of interface modules to provide data transmission paths amongst the end-user devices via the interface modules. The docking station also serves as an accessory for supplying electric power to an end-user device for endurance use.

Abstract: Embodiments of the present disclosure provide a method of storage management and an electronic device. The method of storage management includes collecting information indicating an access error in an access path for accessing a storage device; performing a failure diagnosis on the access path based on the access error, the failure diagnosis including at least one of a first diagnosis related to a topology, a second diagnosis related to a history access error, or a third diagnosis related to a protocol; and providing an output related to health status of the access path based on the failure diagnosis.

Abstract: A pluggable, modular electronic processing component comprises a housing and programmable circuitry. The housing includes a set of conductive terminals that extend therefrom, and each terminal of the set of conductive terminals is sized and spaced to fit into a corresponding terminal socket of a distribution module. The programmable circuitry contained within the housing comprises a processor and a bus interface communicably coupled to the processor. The bus interface interfaces the pluggable, modular electronic processing component to a bus connected to via the distribution module. Further, the bus interface is coupled to a subset of the conductive terminals of the housing. Moreover, the programmable circuitry comprises a configurable input-output (or a set of configurable I/O) that is coupled to a second subset of the conductive terminals of the housing.

Abstract: Systems and methods for automatically provisioning and de-provisioning software defined storage (SDS) systems. Characteristics such as IOPS (Input Output operations per Second), capacity, and throughput of the SDS systems are monitored. Capacity or storage is added or removed from the SDS systems based on the relationships between the characteristics of the SDS systems with respect to upper and lower thresholds.

Abstract: A display device includes a first connector which receives a first image signal and first driving power, a second connector which receives a second image signal and second driving power, a first control unit which processes the first image signal and the first driving power, a second control unit which processes the second image signal and the second driving power, a power management unit which receives the first and second driving powers from the first control unit and the second control unit, measures the first and second driving powers, and provides information about the first driving power and information about the second driving power to the first and second control units, and a display unit which receives one of the first and second image signals from one of the first and second control units and displays one of the first and second image signals.

Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract: A system, method, and apparatus are provided for operating a device to receive a first signaling state sequence on a multi-wire interface within a first voltage range to cause the device to transition to a high-speed communication mode for receiving high-speed data on the multi-wire interface within a second, smaller voltage range before returning to a low-power communication mode when the device receives on the multi-wire interface a second sequence of two signaling states within the first voltage range to signal a turnaround command without requiring any additional signaling state within the first voltage range, where the turnaround command enables the device to transmit data from the device over the multi-wire interface by transmitting on the multi-wire interface the first sequence of signaling states within the first voltage range to cause the device to transition to a high-speed communication mode for transmitting data from the device over the multi-wire interface.

Abstract: A first sequence of transaction control sets (TCSs) collectively describe a first data transfer by which first data is to be moved between a first peripheral and first and second memory buffers. A first portion of the first data is transferred between the first memory buffer and the first peripheral according to a first TCS in the first sequence. Subsequently, a second portion of the first data is transferred between the second memory buffer and the first peripheral according to a second TCS in the first sequence. An actual error detection code is determined based on the first and/or second portions of the first data or an address actually processed during execution of the first and/or second TCSs. An error is selectively flagged based on whether the actual error detection code is the same as an expected error detection code contained in a third TCS in the first sequence.

Abstract: Systems, methods, and devices can involve a host device that includes a root complex, a link, and an interconnect protocol stack coupled to a bus link. The interconnect protocol stack can include multiplexing logic to select one of a Peripheral Component Interconnect Express (PCIe) upper layer mode, or an accelerator link protocol upper layer mode, the PCIe upper layer mode or the accelerator link protocol upper layer mode to communicate over the link, and physical layer logic to determine one or more low latency features associated with one or both of the PCIe upper layer mode or the accelerator link protocol upper layer mode.

Abstract: Sideband device management bus messages are filtered using software operations in order to minimize dropped messages and to maintain the bus in an operable state. Redundant sideband device management buses are utilized in order to provide fail-over transmission of messages in scenarios where one of the buses becomes inoperable. Multi-packet messages are transmitted to managed devices via the sideband bus connections. If an inoperable state is detected in a sideband bus connection during transmission of a multi-packet message, the portion of the multi-packet message not received by the managed device is transmitted via a redundant sideband bus connection with the managed device. Software filtering of bus transactions utilizes a circular DMA buffer for storing all incoming transactions. Transactions of interest are copied to buffers associated with specific endpoints for processing.

Abstract: A security module authentication system includes a processing system that is configured to authenticate a security module based on a processing system type of the processing system. The system also includes a Basic Input/Output System (BIOS) coupled to the processing system and that includes a BIOS storage device. The BIOS storage stores a plurality of security modules each of which corresponds to a different processing system type. The BIOS is configured to utilize any of the plurality of security modules to perform a secure boot. The BIOS storage also stores an image table that identifies a first location in the BIOS storage of a first security module of the plurality of security modules. The first security module is authenticable by the processing system based on the processing system type of the processing system.

Abstract: Some embodiments of the invention provide a novel method and chip design for a forwarding chip, that decouples input-output (IO) technology requirements from the technology used in a high bandwidth switching ASIC. In some embodiments, a main die including a latest generation switching chip is coupled to a set of IO dies (e.g., SerDes dies). The main die, in some embodiments, uses a latest technology (e.g., 7 nm nodes) while the IO dies, in some embodiments, use a more mature technology (e.g., 16 nm nodes). Some embodiments provide multiple IO dies that each provide connectivity to external components to the high bandwidth switching ASIC (e.g., a core ASIC die). The multiple dies are mounted on a silicon interposer, in some embodiments, using microbumps to make the connections between the dies and the silicon interposer. Additional connections to the pad are made from each die including to general purpose input-output (GPIO) connections.

Abstract: Example implementations relate to chipset reconfiguration based on device detection. For example, a method includes detecting, by a computing system, that a storage device is connected to an input/output (I/O) interface of the computing system, and reconfiguring a chipset of the computing system based on the detected storage device. The method also includes performing a power cycle on chipset standby power to trigger a chipset configuration reload.

Abstract: A method of operating a storage device controller which controls a storage device includes receiving a debugging data request command through a peripheral component interconnect express (PCIe) interface of the storage device controller from outside of the storage device controller, and storing debugging data in a register included in the PCIe interface.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes configuring a first interface to exchange data over two primary wires of a serial bus in accordance with a first I3C protocol, and configuring a second interface to communicate over at least one secondary wire in accordance with a second I3C protocol. In one example, the first data is encoded in a sequence of symbols representing signaling state of the two primary wires. A recovered clock signal may be derived from transitions between symbol transmission intervals in the first interface may be used to control double data rate communication through the second interface.

Abstract: A universal serial bus (USB) multi-host device includes a plurality of upstream ports connected to a first host and a second host, a storage for storing data to be transmitted from the first host to the second host through the upstream ports, and a controller, and if the storage receives the data, the controller transmitting a signal based on the received data to the second host, and transmitting the stored data to the second host.

Abstract: An integrated circuit includes a processor to monitor a communication interface arbitration sequence on a system bus, determine, based on the monitored arbitration sequence, a master or slave identifier that is sending a transaction on the system bus, and process the transaction based on the determined master or slave identifier that is sending the transaction.

Abstract: A method for use in deploying computers into a data center includes calculating in a computer an expected peak power draw for a plurality of computers. The expected peak power draw for the plurality of computers is less than a sum of individual expected peak power draws for each computer from the plurality of computers.