Abstract: An input/output (I/O) and control system for long distance communications and industrial applications is provided having a two wire bus and bus protocol for communications between field devices and a channel generator for monitoring and control of the field devices. The channel generator produces an offset square wave on the bus, and sends a synchronization pulse of selected duration at the start of each bus scan cycle in a pulse train cycle to reset counters in the field devices before the bus scan cycle is repeated, to ensure field devices are synchronized, transmitters transmit on the correct channel, and receivers sample the pulse cycle at the correct time. High side and low side current detectors for respective ones of the two wires of the bus and an algorithm are provided to improve detection of valid inbound transmissions by the channel generator for increased noise immunity.

Abstract: Boardroom table systems are provided that include a plurality of USB Type-C receptacles that can provide power and/or data transfer functionality to one or more devices attached thereto. Power transferred by the boardroom table system may be managed by USB Power Delivery, and may come from a source of wall power, or from a device coupled to one of the USB Type-C receptacles. Data transferred by the boardroom table system may include USB data, Ethernet data, video data, and/or any other type of data transmittable via a USB Type-C receptacle. In some embodiments, boardroom table systems also include presentation devices. In such embodiments, a device coupled to a USB Type-C receptacle could both transmit or receive power, exchange data, and transmit video to the presentation device via the same USB Type-C receptacle of the boardroom table system, thus eliminating the need for multiple sockets and cables.

Abstract: The present disclosure describes a control system network architecture for a fluidic control system such as a hydraulic or pneumatic control system. The architecture includes a plurality of clustered control-component nodes with each node being alternatively configurable to independently control the operation of multiple single-acting controlled endpoint devices or a double-acting controlled endpoint device. Each node includes control-components including a solenoid, one or more valve spools independently controllable by the solenoid, and a low-level controller operable to control the solenoid. The solenoid, valve spools, and low-level controller are clustered together and physically co-located as a unit. The nodes are arranged in a control block with each node being uniquely identifiable for data communication via a data communication network. The data communication network may include a Controller Area Network (CAN).

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request. A bucket for the I/O request may be allocated. An offset and mapping information of the I/O request may be written into a log. The offset and mapping information of the I/O request may be written into a tree structure. Garbage collection for the tree structure may be executed to reuse the bucket.

Abstract: A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.

Abstract: A vehicle USB hub system that includes a USB hub, a controller and memory unit is provided. The vehicle USB hub system collects data link quality metrics for messaging to and within a vehicle. The USB hub has a CRC error detector for detecting CRC errors in messaging received via its ports. Information regarding detected CRC errors is stored in the memory unit. The controller generates a CRC error log using the information stored in the memory unit upon receiving an indication that an error log should be sent. The controller then sends the CRC error log to a device via the USB hub port indicated.

Abstract: A cloned configuration of a source machine is created by determining a first set of physical location codes for a source machine. A map is generated based on the sorted physical location codes that maps the first set of physical location codes to a first set of generic location codes. A second set of physical location codes associated with a second set of adapter slots in a target machine is generated. A second map is generated based on the sorted second set of physical location codes that maps the second set of physical location codes to a second set of generic location codes. A third set of physical location codes is generated based on the first set of generic location codes and the second map. If an entry in the third set of physical location codes is not present the second set of physical location codes, an error is generated.

Abstract: A semiconductor system includes a CPU connected to a heterogeneous memory module via a system bus. The heterogeneous memory module includes; a volatile memory module, a nonvolatile memory module, an internal bus separate from the system bus and connecting the volatile memory module and the nonvolatile memory module, and a swap manager configured to control execution of a swap operation transferring target data between the volatile memory module and nonvolatile memory module using the internal bus and without using of the system bus.

Abstract: A device includes multiple communication interfaces configured to send and receive data over multiple communication paths. The device also includes multiple input/output (I/O) channels configured to communicate with multiple field devices. The device further includes at least one processing device configured to process at least some of the data and control at least one of the field devices based on the processed data. The device may also include an intrinsic safety barrier electrically separating the communication interfaces and the I/O channels. The communication interfaces may include at least one first interface configured to communicate over one or more first communication paths with at least one component of an industrial control system and at least one second interface configured to communicate over one or more second communication paths with at least one other device that is configured to communicate with additional field devices.

Abstract: A method, computer program product, and computer system for receiving, by a computing device, an I/O request, wherein the I/O request may include host I/O priority information. It may be determined that the I/O request is associated with a token bucket of a plurality of token buckets based upon, at least in part, the host I/O priority information. If the token bucket of the plurality of token buckets has sufficient tokens for the I/O request, the I/O request may be sent down a block stack for processing, and if the token bucket of the plurality of token buckets has insufficient tokens for the I/O request, the I/O request may be rejected.

Abstract: Disclosed are a memory device, a memory package including the same, and a memory module including the same. The memory package includes a first memory device configured to operate in response to a first chip select signal from an external device, a second memory device configured to operate in response to a second chip select signal from the external device, and a third memory device configured to operate in response to a third chip select signal from the external device. The third memory device includes a buffer unit that is connected with an internal circuit of the third memory device through an internal data line, is connected with the first memory device through a first memory data line, is connected with the second memory device through a second memory data line, and is connected with the external device through a data line.

Abstract: A Main Logic Board having an electrically configurable option board interface (ECOBI) to facilitate connection of option boards into apparatus for providing optional functions. Once connected to the host, an Option board provides identification (ID) data to the main logic board host processor. The host processor determines the interface configuration necessary to enable communication between the host and the option board based on the option board ID, then configures electrically configurable interface circuitry for operational compatibility. The option board may provide an interface driver directly to the host for configuration of the interface. The interface may comprise a standard interface protocol such as PCI or USB that the host configures through the same connection to the option board.

Abstract: A queue manager apparatus converts inbound commands of a first width into scalar format commands to be queued in a command queue. Furthermore, the queue manager converts the scalar format commands residing in the command queue into outbound commands of a second width for transmission. Converting inbound commands to scalar format commands and then converting the scalar format commands to a target width for transmission allows the queue manager to advantageously provide efficient and programmable command transmission between arbitrary processing units, regardless of potentially mismatched native command widths.

Abstract: The invention introduces an apparatus for accessing a memory card to at least include a host interface and a processing unit. The processing unit is arranged to operably inspect whether a logical block length utilized in a memory card inserted into a card reader can be supported by a host; and reply to the host with sense data that advises the host not to perform a subsequent write into the memory card through the host interface in response to a request sense command when the logical block length utilized in the memory card cannot be supported by the host.

Abstract: Implementations described and claimed herein provide a method and system for detecting slow storage drives. In one implementation, the method includes dynamically creating a storage drive peer group including a plurality of storage drives, comparing performance statistics of the storage drives in the storage drive peer group, selecting an outlier storage drive of the storage drive peer group based on the comparison of the performance statistics, passively monitoring response times of the storage drives in the storage drive peer group, comparing average response times of the storage drives in the storage drive peer group, flagging an outlier storage drive of the storage drive peer group with an outlier storage drive designation responsive to comparison of the average response times, actively measuring workload metrics of the outlier storage drive, comparing workload metrics data of the outlier storage drive to workload metrics reference data, and performing a remedial action.

Abstract: A storage medium storing a device driver is a storage medium storing a device driver executed by a computer to control communication between the computer and a peripheral device connected to the computer, and a process for matching a first characteristic and a second characteristic is executed by the device driver, with respect to information transmitted and received between the application software and the peripheral device, on the basis of first information and second information acquired from the peripheral device.

Abstract: A network system includes a central processing unit and a peripheral device in electrical communication with the central processing unit. The peripheral device has at least one power input and a data input. The network system also includes an out of band controller in electrical communication with the central processing unit, the peripheral device, and an external management interface. Responsive to an identified threat, the out of band controller is configured to disable the at least one power input and the data input to the peripheral device, where the disablement indicates to the central processing unit that a hot plug event has occurred with respect to the peripheral device. The out of band controller is also configured to enable auxiliary power to the peripheral device such that the out of band controller remains in communication with the peripheral device during remediation of the identified threat.

Abstract: A method for controlling a dongle device to enter a waiting state of device pairing to perform automatic device pairing includes: commanding the dongle device to enter the waiting state when the dongle device is powered up, the dongle device having a storage circuit which is used for storing specific information of at least one electronic device that has been paired with the dongle device; checking the storage circuit of the dongle device; and transmitting a pairing request from the dongle device to the electronic device according to a result of checking the storage circuit.

Abstract: A method of real-time data acquisition in a processing component using chained direct memory access (DMA) channels includes receiving a DMA event signal in a DMA controller of the processing component, and executing, responsive to the DMA event signal, DMAs to read at least one data sample from a peripheral device. A last DMA performs a write operation to acknowledge completion of the DMA event.

Abstract: A system includes an array of counter/timer units that execute a number of timing and pattern generation functions that are selectable by a processor to which the array is coupled. Counter/timer units may receive as inputs the outputs of other counter/timer units, such as for use as a trigger or clock input as instructed by the processor. Counter/timer units may be instructed to execute functions and be coupled to one another by a processor. The processor may then enable the counter/timer units such they subsequently produce complex outputs without additional inputs from the processor. The outputs of the counter/timer units may be used as interrupts to the processor or be used to drive a peripheral device.