Abstract: An electronic apparatus includes: an enlargement and reduction unit that enlarges or reduces an image input by direct memory access (DMA) transfer; and an image processing unit that, in a case where a size of an image after processing for enlargement or reduction by the enlargement and reduction unit is different from a size determined in advance as a size of an image after the processing, performs processing for adding pixels to the processed image or processing for deleting pixels of the processed image.

Abstract: Disclosed aspects relate to a first-in-first-out (FIFO) buffer. The FIFO buffer may include an input interface to receive a set of data payloads. The FIFO buffer may include a set of buffer entry elements to store the set of data payloads. The FIFO buffer may include a set of status indicators to indicate a set of statuses of the set of buffer entry elements with respect to the set of data payloads. The FIFO buffer may include an output interface for release of the set of data payloads.

Abstract: A display device includes a first connector which receives a first image signal and first driving power, a second connector which receives a second image signal and second driving power, a first control unit which processes the first image signal and the first driving power, a second control unit which processes the second image signal and the second driving power, a power management unit which receives the first and second driving powers from the first control unit and the second control unit, measures the first and second driving powers, and provides information about the first driving power and information about the second driving power to the first and second control units, and a display unit which receives one of the first and second image signals from one of the first and second control units and displays one of the first and second image signals.

Abstract: Various embodiments concern techniques for intelligently switching between multiple sources of USB signals. More specifically, user devices are described that include a physical USB port for receiving a USB connector and one or more wireless transceivers that communicate with an accessory. The wireless transceiver(s) may communicate with the accessory using a USB-based protocol (e.g., Wireless USB). The user devices described herein can intelligently switch between these different sources of USB signals so that USB signals can be simultaneously or sequentially received from a peripheral (via the USB port) and an accessory (via the wireless transceiver(s)). In some embodiments, a switching routine is executed (e.g., by a processor or signal switch) that determines which peripheral and/or accessory is connected to a user device at a given point in time.

Abstract: In one embodiment, a storage system receives a number of input/output (IO) request transactions at the storage system having multiple storage devices. The system detects storage events associated with the storage devices, the storage events include storage device error events, storage device path error events, and solid state storage device high write amplification events. For each of the IO request transactions, the system tags a number of associated child IO requests with a tag identifier and predicts a completion time for the IO request transaction based on a completeness of the IO request transaction and detected events associated with the storage devices. The system sends the child IO requests to the storage devices to be serviced in a first order based on the predicted completion time and an arrival time of the IO request transaction so that the IO request transactions are resilient to storage events.

Abstract: The disclosed invention is to provide a semiconductor device enabling it to access an internal device within a USB cable in a simple way. Disclosed is a semiconductor device which is able to be coupled to at least one USB cable and which includes a decision unit that decides whether or not an opposite-end device is detected through the USB cable; and a control unit that, if the decision unit has judged that the opposite-end device is not detected through the USB cable, supplies one of two signal lines which are coupled to an internal device within the USB cable with a power supply voltage and implements control of communication with the internal device within the USB cable through the other one of the signal lines.

Abstract: A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.

Abstract: A data transform method and a data transformer. The method includes: importing a data transform rule; acquiring from the data transform rule a source data definition, a destination data definition and a data transform rule definition; predicting resource energy consumption parameters of a data transform node server according to the source data definition, the destination data definition and the data transform rule definition; and deploying a resource energy consumption optimization policy of the data transform node server according to the predicted resource energy consumption parameters of the data transform node server.

Abstract: A real-time operating system (OS) for an embedded system may be configured for asynchronous handling of input and output (I/O) operations. When application code is executing, the OS may be configured to register I/O interrupts and queue I/O operations. When no application code is executing, the OS may be configured to call appropriate interrupt handlers. As result, the OS may maintain the real-time execution that may be required of applications on an embedded system while providing the flexibility and scalability offered by an operating system.

Abstract: An information handling system includes a central processing unit, which in turn includes a system memory and a first processor core. The system memory stores Common Platform Error Record (CPER) entries in a queue. The first processor core stores the hardware error in a bank of a machine check bank register of the first processor core, and generates a system management interrupt (SMI) in response to storing the hardware error in the bank. The central processing unit receives the generated SMI, clears CPER entries within the queue of the system memory that are outside a specific timespan before a corrected machine check error indication associated with the generated SMI is received, adds a CPER entry associated with the corrected machine check error indication to the queue of the system memory, and disables SMI generation from the machine check bank number in response to the number of CPER entries exceeding the threshold count.

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract: A data storage system includes: a plurality of data storage devices; a motherboard containing a baseboard management controller (BMC); and a network switch configured to route network traffic to the plurality of data storage devices. The BMC is configured to identify a group of data storage devices among the plurality of data storage devices based on device-specific information received from the plurality of data storage devices and send identifiers of the group of data storage devices to a querying party.

Abstract: An electronic device includes a case containing a universal serial bus (USB) transmission port, an embedded control unit, a central processing unit, a power supply unit and a multiplex control unit. The multiplex control unit has a first usage mode and a second usage mode. The multiplex control unit is normally in the first usage mode, and switches to the second usage mode when a switch signal is received. In the first usage mode, the multiplex control unit is powered by the power supply unit, and the multiplex control unit builds up a first transmission path between the central control unit and the USB transmission port. In the second usage mode, the multiplex control unit is powered by an external device connected to the USB transmission port, and the multiplex control unit builds up a second transmission path between the embedded control unit and the USB transmission port.

Abstract: In various embodiments, a configurable hardware accelerator is provided. The configurable accelerator may include a transmit direct memory access (DMA) engine, a receive DMA engine, and one or more execution engines. In those embodiments, the configurable accelerator can be configured to access a shared data storage in a continuous mode. The transmit and receive DMA engines can be configured to transmit data from one location in the shared data storage to a different location in the memory storage. The execution engine(s) can be configured to perform a wide range of functions on the data accessed by the transmit DMA engine(s) in streaming fashion. In those embodiments, the data are accessed and processed by the configurable accelerator in a streaming manner to speed up the data processing performance.

Abstract: An apparatus includes a buffer and a processor. The buffer contains a plurality of commands pending for a data storage medium. The processor is configured to sort the commands in an execution efficiency favorable manner, which reveals a most favorable command for execution, compare a skip count for each of the commands to a threshold count, the skip count corresponding to a number of times execution of the command has been skipped in favor of execution of another command, and execute one of the commands having a skip count that has reached the threshold count over the execution of the most favorable command.

Abstract: A communication apparatus includes a first communicator configured to receive signals of a plurality of standards containing a first network signal as a transmitted and received signal for a network, a second communicator configured to receive a second network signal as a transmitted and received signal for the network, a selector configured to select one of the first and second network signals, and a controller configured to control the first and second communicators and the selector. The first communicator includes a first confirmer configured to confirm a reception of the first network signal among the signals of the plurality of standards for the first communicator, and a first operation mode setter configured to set an operation mode to the first communicator.

Abstract: A location-based address adapter for use in a system to facilitate communication between a host computer and one peripheral device of a plurality of peripheral devices includes a body and an electrical circuit. The body is removably attached to one peripheral device at a time. The electrical circuit includes a communications interface circuit and an adapter memory circuit. The communications interface circuit has a respective pass-through wired connection between each of a plurality of input connectors and a plurality of output connectors to facilitate bi-directional communications between the host computer and the peripheral device. The adapter memory circuit stores a unique physical location address for association with a physical location associated with the peripheral device to which the body is attached. The unique physical location address is a non-network based address.

Abstract: An apparatus includes a pass-through module that includes connector pins to connect with at least one active motherboard connector and to separately connect with at least one routing motherboard connector. A routing function on the pass-through module redirects a set of bidirectional lanes from the connector pins connected to the active motherboard connector to the connector pins connected to the routing motherboard connector to enable a connection of the set of bidirectional lanes to at least one other motherboard connector via the routing motherboard connector.

Abstract: An electronic apparatus that is capable of checking connection between the electronic apparatus body and accessories without performing communication between the electronic apparatus body and accessories. The electronic apparatus is capable of communicating with an accessory device connected. A detection unit detects whether the accessory device supports both a first communication method and a second communication method of which communication speed is higher than communication speed of the first communication method. A setting unit sets the second communication method during communication when the detection unit detects that the accessory device supports both the first communication method and the second communication method, and to set the first communication method except communicating.

Abstract: Implementations of the present disclosure involve a system and/or method for managing a storage system and, more particularly, for externally managing input/output (I/O) requests to a storage device to avoid large delays in servicing the I/O requests. The management system may maintain I/O request queues for one or more of the storage devices associated with the system. The system may calculate a difference between an order value of the I/O request at the top of the queue and the bottom of the queue for the storage devices. If the calculated difference is above a threshold value, new I/O requests for the storage device are not added to the queue or transmitted to the storage device. In this manner, the management system may force the storage device to service an I/O request that has been stored in the queue for some time without being serviced.