Abstract: An input-output device includes an input circuit unit including an input-signal-setting storing unit that stores a plurality of ON conditions of the input signal and an input circuit that determines whether any one of the ON conditions of the stored input signal holds, a computing unit including an output-signal-setting storing unit that stores information in which the ON conditions of the input signal, output ports for outputting an output signal, and specifications of the output signal are associated and an output-signal selecting unit that generates, on the basis of a determination result of the input circuit and the stored information, an output command indicating the output ports and the specifications of the output signal, and an output circuit unit including an output circuit that outputs, to the output ports indicated by the output command, the output signal according to the specifications indicated by the output command.

Abstract: Examples of techniques for processing I/O operations in a channel are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: copying, by a system assist processor, a subchannel of the channel into a lower portion of a channel communication area responsive to receiving the I/O operation; copying, by the system assist processor, channel program information from a designated starting location in a customer memory into a control block; building, by the system assist processor, a starting channel communication area into a top portion of the control block; queuing, by the system assist processor, the control block to a queue for the channel; processing, by the channel, the I/O operation responsive to retrieving the control block from the queue.

Abstract: A supersequence is generated that includes a sequence including an electrical ordered set (EOS) and a plurality of training sequences. The plurality of training sequences include a predefined number of training sequences corresponding to a respective one of a plurality of training states with which the supersequence is to be associated, each training sequence in the plurality of training sequences is to include a respective training sequence header and a training sequence payload, the training sequence payloads of the plurality of training sequences are to be sent scrambled and the training sequence headers of the plurality of training sequences are to be sent unscrambled.

Abstract: Techniques for performing compression operations on persistently-stored data blocks during read/write commands. A method embodiment performs in-line data compression operations over data blocks referenced by a caller. The in-line data compression operations are performed during execution of a storage input-output (I/O) command, between the event of receipt of the storage I/O command and the event of returning status of the storage I/O command. The storage I/O operation is associated with at least one data group comprising one or more data blocks that are identified by the caller. Upon receipt of the storage I/O command, one or more compression rules are applied to the data blocks to determine one or more compression parameters, which compression parameters are used to form specific compression operations that are performed over at least a portion of the data group. The status pertaining to the execution of the storage I/O operation is returned to the caller.

Abstract: A method of determining which of at least two connected mobile devices is to function as a host device, wherein the mobile devices first determine which of them is to act as an initial host device and which is to act as an initial peripheral device. The initial host device then receives instructions from a user as to which of the mobile devices is to be the host device. If the instructions indicate that the initial host device is to be the host device, the initial host device controls, as host device, the initial peripheral device as a peripheral device, and if the instructions indicate that the initial peripheral device is to be the host device, the initial host device passes control to the initial peripheral device to enable the initial peripheral device to control, as host device, the initial host device as a peripheral device.

Abstract: In some embodiments, a DMA controller includes a set of transaction control registers configured to receive a linked list sequence of transaction control sets. The transaction control sets collectively describe a data transfer by which the DMA controller is to move data from a peripheral alternatingly to a first memory buffer and a second memory buffer, wherein the first and second memory buffers are arranged in parallel with one another at an interface of the peripheral. The DMA controller is configured to transfer a first set of data from the peripheral to the first memory buffer according to a first transaction control set in the linked list sequence, and is configured to subsequently transfer a second set of data from the peripheral to the second buffer according to a second transaction control set in the linked list sequence.

Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.

Abstract: A method and device for transmitting and receiving data using HDMI (High-Definition Multimedia Interface) are disclosed. The method, if performed by a source device, includes: receiving a request from a sink device to transmit data processing capability information indicating whether the source device is capable of processing user-input data or not; transmitting the data processing capability information to the sink device; and receiving the user-input data from the sink device.

Abstract: An operating system includes an interrupt router that dynamically steers each interrupt to one or more processors within set of processors based on overall load information from the set of processors. An interrupt source is assigned to a processor based on the load imposed by the interrupt source and the target overall load for the processor. For example, each processor can maintain information about each interrupt it processes over time. The operating system receives this historical load information to determine an expected load for interrupts of a given type from a given device, an overall load on the system, and a target load for each processor. Given a set of interrupt sources, their expected loads, and target load for each processor, each interrupt source can be assigned dynamically to a processor during runtime of the system. These assignments can be changed given current operating conditions of the system.

Abstract: A data processing system includes, in one embodiment, at least a first processor and a second processor and an interrupt controller, and the system provides a deferred inter-processor interrupt (IPI) that can be used to wake up the second processor from a low power sleep state. The deferred IPI is, in one embodiment, delayed by a timer in the interrupt controller, and the deferred IPI can be cancelled by the first processor if the first processor becomes available to execute a thread that was made runnable by an interrupt which triggered the deferred IPI.

Abstract: Systems and methods for automatically provisioning and de-provisioning software defined storage (SDS) systems. Characteristics such as IPOS, capacity, and throughput of the SDS systems are monitored. Capacity or storage is added or removed from the SDS systems based on the relationships between the characteristics of the SDS systems with respect to upper and lower thresholds.

Abstract: Various techniques are provided to efficiently implement user designs incorporating clock and/or data recovery circuitry and/or a deserializer in programmable logic devices (PLDs). In one example, a method includes receiving a serial data stream, measuring time periods between signal transitions in a serial data stream using at least one Grey code oscillator, and generating a recovered data signal corresponding to the serial data stream by, at least in part, comparing the measured time periods to one or more calibration time periods. In another example, a system includes a Grey code oscillator configured to increment a Grey code count between signal transitions in a serial data stream, and a Grey code converter configured to convert the Grey code count approximately at the signal transitions to a plurality of binary counts each corresponding to a time period between one or more signal transitions in the serial data stream.

Abstract: A CAN module comprising a bit duration compensation component arranged to generate a compensated transmit command signal for controlling the driver component to drive a dominant state on the CAN bus. The compensated transmit command signal comprises dominant bits of a compensated-bit duration Tbit_cp=Tbit_Tx+tc, wherein tc comprises a compensation offset derived at least partly from a difference between a transmit-bit duration of a digital transmit command signal and a receive-bit duration of a received data signal.

Abstract: An IO subsystem chassis includes IO modules and IO slots to receive the IO modules inserted from a frontend of a housing, a baseboard disposed within the housing, the baseboard including first connectors corresponding to the IO slots to receive and connect the IO modules. Each of the IO modules can be coupled a server via the backend panel using a cable. Each IO module includes an IO card having a peripheral device mounted thereon and a card holder having a first receiving socket to receive and hold the IO card plugged in vertically and downwardly. The card holder further includes a second connector to engage with or disengage from a corresponding one of the first connectors of the baseboard horizontally, when the IO module is inserted into or removed from a corresponding IO slot from the frontend, without having to removing the housing.

Abstract: Systems and methods are presented for detecting, by a universal serial bus (USB) drive operatively coupled with a computing device, power from the computing device, and determining, by the USB drive, that drivers associated with the USB drive have been installed on the computing device. The systems and methods may determine that drivers associated with the USB drive have been installed by sending, to the computing device, a digital signal indicating a predetermined keystroke until the USB drive receives a response from the computing device, and receiving, from the computing device, a feedback response to the digital signal indicating the predetermined keystroke has been received. The systems and methods further executing, by the USB drive, a macro to download a payload to the computing device from a server computer, causing by the USB drive, the payload to execute on the computing device, and causing, by the USB drive, the downloaded payload to be deleted from the computing device.

Abstract: Apparatus and methods for digital bus operation. In one embodiment, the digital bus is a bidirectional, time-division multiplexing (TDM) audio bus operation, and a bus technology is described that enables multi-drop (e.g., multiple device, multiple node, etc.) connectivity for real-time audio over a small form factor interface (e.g., as few as two (2) wires). Specifically, an exemplary tri-level signaling scheme provides bidirectional functionality, real-time clock edges, audio data, in a multi-drop topology in one implementation.

Abstract: A USB communication control method, in which a USB host and a USB accessory executing an Android operating system are connected to each other through a USB cable, includes: when an application is executed on the USB accessory, acquiring USB connection information between the USB host and the USB accessory by the application; when the application being executed on the USB accessory is completed, initializing an Android Open Accessory Protocol (AOAP) of the USB accessory by the application by assigning USB control authority to the application; changing the USB connection information between the USB host and the USB accessory to information of a state before the completion of the application; and resuming USB communication between the USB accessory and the USB host.

Abstract: A technique for handling cache-inhibited operations in a data processing system includes receiving, at a topology specific replicated bus unit, a cache-inhibited (CI) operation that is scope limited. The replicated bus unit determines whether an address associated with the CI operation matches an address for the replicated bus unit. In response to the address associated with the CI operation matching the address for the replicated bus unit, the replicated bus unit processes the CI operation based on the scope being limited to that of the replicated bus unit. In response to the address associated with the CI operation not matching the address for the replicated bus unit, the replicated bus unit ignores the CI operation.

Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.

Abstract: Amplifiers, preamplifiers, and other circuits may have registers that are assigned to store data corresponding to certain functions. When the data stored in the registers are no longer needed, the registers may be assigned to store data corresponding to other functions, such as signal acquisition. The registers can be logically grouped into a virtual memory bank. The memory bank may store new data to a first register, and move data from the first register to a second register when new data arrives. In some embodiments, these registers and memory control circuit can be implemented within a preamplifier circuit.