Abstract: Various embodiments are generally directed to an apparatus, method and other techniques to determine whether a target address of a register for an execution instruction is valid or invalid based on a comparison between the target address and one or more valid target addresses stored in a storage, increase a number of invalid target addresses if the target address is invalid, and determine whether the number of invalid target addresses is greater than an invalid target address threshold. Various embodiments may also include initiating a security measure to prevent a security breach if the number of invalid target addresses is greater than the invalid target address threshold or executing the execution instruction if the number of invalid target addresses is less than or equal to the invalid target address threshold.

Abstract: An apparatus for transceiver multiplexing over USB Type-C interconnects is described herein. The apparatus includes a processor, a memory, a USB Type-C connector, a first transmitter, a multiplexed transmitter, a multiplexed receiver, and an on-die inductor. The multiplexed transmitter, when disabled, enables the multiplexed receiver to be in communication over a channel with a second transmitter over the USB Type C connector. The multiplexed receiver, when disabled, enables the multiplexed transmitter to be in communication over the channel with a receiver over the USB Type-C connector. The on-die inductor is disposed in serial with the multiplexed transmitter, and disposed in parallel with the multiplexed receiver. The on-die inductor reduces: effective shunt capacitance and insertion loss between the multiplexed transmitter and the channel; effective shunt capacitance and insertion loss between the channel and the multiplexed receiver.

Abstract: An intelligent connector is disclosed having a signal processing unit, a first port, and a second port. The signal processing unit communicates signals between a bus and a slave module. The first port is coupled between the bus and the signal processing unit, and is connected to a power supply line. The second port is coupled between the signal processing unit and the slave module, and is positioned to provide a power supply to the slave module.

Abstract: Generally, this disclosure describes systems (and methods) of moderating interrupts in a virtualization environment. An overflow interval is defined. The overflow interrupt interval is used to trigger activation of an inactive guest so that the guest may respond to a critical event. The guest, including a network application, may be active for a first time interval and inactive for a second time interval. A latency interrupt interval may be defined. The latency interrupt interval is configured for interrupt moderation when the network application associated with a packet flow is active, i.e., when the guest including the network application is active on a processor. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A Universal Armament Interface (UAI) translator for a legacy military standard-1760 (MIL-STD-1760) messaging interface can include a legacy interface, a UAI, and a processor. The legacy interface can transmit a legacy receive message (‘R’ message) and receive a legacy transmit message (‘T’ message). The legacy interface can include a MIL-STD-1760 remote terminal (RT) messaging interface. The UAI can receive a UAI ‘R’ message and transmit a UAI ‘T’ message. The processor can translate the legacy ‘R’ message to the UAI ‘R’ message, and translate the UAI ‘T’ message to the legacy ‘T’ message.

Abstract: A microcontroller includes a general purpose input/output (GPIO) port having a plurality of bits coupled to a plurality of external pins; a first set of registers for providing at least one of first control and data input/output functionality of the GPIO port; a second set of registers for providing at least one of second control and data input/output functionality of the GPIO port; and a multiplexer and associated select register for controlling the multiplexer to control said GPIO port through either said first or second register set.

Abstract: One feature pertains to an advanced computer device configured for storing data on a plurality of non-volatile memory mass storage devices. The mass storage devices may interface with the computer device through a plurality of base boards mounted in an enclosure that are configured to couple with at least one non-volatile memory storage drive. Each base board may further be configured to couple with a high speed interconnect cable to exchange data to be loaded or stored with the computer device. According to one aspect, the high speed cable transfers Serially Attached SCSI (SAS) or PCIe data packets or frames.

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract: A method, signal conditioning circuit, and system are disclosed to perform signal conditioning using a processing component coupled with at least first and second inputs. The processing component is further coupled with a first output port including first and second data lanes operable at different data rates. The method includes receiving, via the first input and at a first data rate, data included in a first input signal, and receiving, via the second input and at a second data rate different from the first data rate, data included in a second input signal. The method further includes driving, based on the first and second input signals, a first output signal onto the first output port, which includes transmitting the data included in the first input signal on the first data lane, and transmitting the data included in the second input signal on the second data lane.

Abstract: A method of receiving a broadcast service is provided. The method includes receiving uncompressed audio or video content, obtaining information regarding a channel of the uncompressed audio or video content on the basis of a part of the uncompressed audio or video content, and obtaining content and trigger information for the broadcast service by using the obtained information.

Abstract: Various embodiments concern techniques for intelligently switching between multiple sources of USB signals. More specifically, user devices are described that include a physical USB port for receiving a USB connector and one or more wireless transceivers that communicate with an accessory. The wireless transceiver(s) may communicate with the accessory using a USB-based protocol (e.g., Wireless USB). The user devices described herein can intelligently switch between these different sources of USB signals so that USB signals can be simultaneously or sequentially received from a peripheral (via the USB port) and an accessory (via the wireless transceiver(s)). In some embodiments, a switching routine is executed (e.g., by a processor or signal switch) that determines which peripheral and/or accessory is connected to a user device at a given point in time.

Abstract: The first buffers forward data from the first device to the respective corresponding second devices through the respective buses while the second buffers forward data from the respective corresponding second devices to the first device through the respective buses. In response to a simultaneous data transmission request to simultaneously transmit data from the first device to the second devices, the switch controller switches the first buffer into a data-forwarding enable state, and switches the second buffer into a data-forwarding disable state, for simultaneous data transmission from the first device to the plurality of the second devices. The pseudo-response generator generates pseudo-response signals acting as a plurality of response signals that the second devices transmit to the first device as a result of the simultaneous data transmission, and transmits the plurality of the pseudo-response signals to the first device. This configuration achieves simultaneous access to multiple devices.

Abstract: An electronic device connected to numerous first load medias and second load medias. The electronic device comprises a processor and a switch module. The processor is capable of switching between a first working mode and a second working mode. Under the second working mode, the processor generates a second control signal, the switch mode establishes independent electronic connections between specified first load medias and specified second load medias, thus, the first load medias and the second load medias simultaneously communicate with each other through the electronic device.

Abstract: An information processing system includes: an information processing apparatus; and a terminal device configured to communicate with the information processing apparatus using a connection established between the information processing apparatus and the terminal device. The information processing apparatus notifies the terminal device of scheduled time of release of the connection, and the terminal device determines whether or not current time has passed the scheduled time notified from the information processing apparatus at the time of transmitting a request to the information processing apparatus and, in a case where the current time is determined to have passed the scheduled time, before transmitting the request to the information processing apparatus, transmits a connection request for establishing a connection with the information processing apparatus to the information processing apparatus.

Abstract: A method and apparatus are provided for implementing modal selection of a bimodal coherent accelerator in a computer system. Implementing modal selection of a bimodal coherent accelerator using a PCI-Express standard Vendor Specific Extended Capability (VSEC) structure or CAPI VSEC data in the configuration space of a CAPI-capable PCIE adapter and procedures defined in the Coherent Accelerator Interface Architecture (CAIA) to enable and control a coherent coprocessor adapter over PCIE. A CAPI-capable PCIE adapter is enabled to be bimodal and operate in conventional PCI-Express (PCIE) transaction modes or CAPI modes that utilize CAIA coherence and programming interface capabilities.

Abstract: A gateway apparatus (103) receives a request frame transmitted from a system controller (101) to an indoor unit 1 (111), and determines whether a sensor specified in the request frame is a sensor 1-A (121) which is connected with the indoor unit 1 (111) or a sensor 1-B (123) which is not connected with the indoor unit 1 (111). When the sensor specified in the request frame is the sensor 1-B (123), the gateway apparatus (103) acquires a measurement value from the sensor 1-B (123), and responds to the system controller (101) with the acquired measurement value of the sensor 1-B (123).

Abstract: A method of transmitting universal serial bus (USB) frames over a communications channel is disclosed. A USB device receives one or more USB frames from a host device via a network, wherein the one or more USB frames are encapsulated in one or more data packets based on a communications protocol associated with the network. The USB device further synchronizes a local clock signal with a clock signal of the host device using a clock synchronization mechanism of the communications protocol. The USB device then determines a number of USB frames transmitted by the host device and processes the one or more USB frames based, at least in part, on the synchronized local clock signal. For some embodiments, the USB device may receive a frame count value and a corresponding media time value from the host device.

Abstract: In one example, a method includes determining, by a wireless dockee (WD), one or more wireless docking environments (WDNs) associated with a wireless docking center (WDC), wherein each WDN of the one or more WDNs corresponds to at least one peripheral function (PF) of one or more PFs that are each associated with the WDC. In this example, the method also includes wirelessly accessing, by the WD, a respective at least one PF corresponding to a particular WDN of the one or more WDNs associated with the WDC.

Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.

Abstract: A device for manipulating interface signals includes a slave interface, which is connectable to a master interface of a control device, a master interface, which is connectable to a slave interface of a measuring device, and a circuit configuration, which is supplied with at least one data-input signal per interface, and which outputs a corresponding data-output signal per data-input signal to the respective other interface. The circuit configuration includes at least one manipulation unit, to which a data-input signal and a substitute-data signal are supplied and which outputs a corresponding data-output signal, as well as a protocol unit, to which at least one protocol-relevant interface signal is supplied and which, based on manipulation rules and information received with the at least one protocol-relevant interface signal, chooses when the at least one manipulation unit outputs the corresponding data-input signal or the substitute-data signal as data-output signal.