Abstract: Described is a voltage regulator with feed-forward and feedback control. Described is an apparatus which comprises: a circuit for providing power or ground supply for a target circuit in response to a control signal; and a feed-forward filter to receive data and to generate the control signal according to the received data.

Abstract: An information processing system includes a receiving unit that receives user operation; a setting unit that holds association information in which pieces of necessity information each indicating necessity of a shutdown process indicating a process required for stopping power supply to a corresponding device are associated with a plurality of devices, respectively; a first instruction unit that instructs a target device for which the power supply is to be stopped to perform the shutdown process when the receiving unit receives operation to stop the power supply and the target device requires the shutdown process based on the association information; and a second instruction unit that instructs a power supply control device that controls execution or stop of the power supply to the target device to stop the power supply to the target device when the shutdown process of the target device is completed.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include a processor and a management controller communicatively coupled to the processor and configured to, during boot of the information handling system determine a first amount of energy required by the information handling system to perform a save operation to transfer data from a volatile memory to a non-volatile memory of a persistent memory in response to a loss of power for supplying electrical energy to the information handling system, determine whether a second amount of energy available for providing electrical energy for the save operation in response to the loss of power exceeds the first amount of energy, and responsive to determining whether the second amount of energy exceeds the first amount of energy, determine whether to support the persistent memory.

Abstract: According to one embodiment, a processor includes an instruction decoder to decode instruction and a execution unit to execute instructions, the execution unit being associated with a capture logic to periodically capture operating heuristics of the execution unit, a detection logic coupled to the execution unit to evaluate the captured operating heuristics to determine whether there is a need to adjust an operating point of the execution unit, and a control logic coupled to the detection logic and the execution unit to adjust the operating point of the execution unit based on the evaluation of the operating heuristics.

Abstract: An integrated circuit is provided with a low-power island including embedded memory power domains that may selectively couple to either an active-mode power supply voltage supplied on a first power rail or to a sleep-mode power supply voltage supplied on a second power rail.

Abstract: Following a restart or a reboot of a system that includes a multi-core processor, the multi-core processor may assign one of the cores as a boot strap processor (BSP). Initialization logic may detect a state of each of the plurality of processing cores as active or inactive. The initialization logic may detect an attribute of each of the plurality of processing cores as eligible to be assigned as a BSP or as ineligible to be assigned as the BSP. The initialization logic may detect a last processing core of the plurality of processing cores in the interconnect that is an active processing core based at least in part on the state and is eligible to be assigned as the BSP based at least in part on the attribute. In various embodiments, the initialization information may assign the last processing core as the BSP.

Abstract: Disclosed is an operating method of an electronic apparatus. The method includes measuring the load rate of the electronic apparatus that operates at the first driving frequency level. The method also includes determining a second driving frequency level based on the measured load rate. The method further includes determining whether or not to change the first driving frequency level into the second driving frequency level after the operational duration time of the first driving frequency level. The method includes based on determining the change from the first driving frequency level to the second driving frequency level, controlling to operate at the first driving frequency level or the second driving frequency level.

Abstract: A device for reconfigurable power conversion includes a plurality of power-consuming modules adapted to receive a plurality of electrical voltages, and a power converter module including a plurality N of power stages, each of which includes a power output which is adapted to supply one of the plurality of electrical voltages and adapted to be coupled with at least one of the others of the power outputs off the power converter module. Also included is a backplane including a plurality of power rails, each of which is adapted to distribute one of the plurality of electrical voltages from the power converter module to the plurality of power-consuming modules. The power converter module further includes a programmable converter controller which is adapted to reversibly configure the plurality of power stages.

Abstract: The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.

Abstract: Described is an apparatus which comprises: an input for providing a first voltage signal; a level translator, coupled to the input, to translate the first voltage signal to a second input voltage, the second input voltage having a voltage level higher than a voltage level of the first voltage signal; and an open loop reference core coupled to the level translator, the open loop reference core to receive the second input voltage and to generate an output indicating whether the first voltage signal is above or below a reference level.

Abstract: A performance setting technique is disclosed for a clocked circuit such as a processor in an integrated circuit. The technique determines a maximum power consumption for the clocked circuit as a function of a total thermal resistance of a mobile device incorporating the integrated circuit. The total thermal resistance is a sum of a system thermal resistance for the mobile device and a device thermal resistance for the integrated circuit.

Abstract: The present invention provides a communication system including a relay device that is capable of simplifying the configuration of a control device for controlling a device based on relay information and reducing cost of the whole system, the relay device and a method for controlling power supply. A GW device includes first to fourth communication parts respectively connected to communication buses, which are connected to ECUs respectively. The GW device receives a message transmitted from each of ECUs, extracts signal information S1 to S5 related to equipment in the vehicle included in the message from the received message, collects the extracted signal information S1 to S5 to create a message (ID4), and transmits the created message to a power supply control device. The power supply control device controls on/off of the ECUs and each of loads based on signal information included in the message received from the GW device.

Abstract: Methods and apparatus relating to controlling processor slew rates based on battery charge state/level are described. In one embodiment, logic causes modification to a slew rate of a processor based on at least a charge level of a battery pack. Other embodiments are also disclosed and claimed.

Abstract: A device for reconfigurable power conversion includes a plurality of power-consuming modules adapted to receive a plurality of electrical voltages, and a power converter module including a plurality N of power stages, each of which includes a power output which is adapted to supply one of the plurality of electrical voltages and adapted to be coupled with at least one of the others of the power outputs off the power converter module. Also included is a backplane including a plurality of power rails, each of which is adapted to distribute one of the plurality of electrical voltages from the power converter module to the plurality of power-consuming modules. The power converter module further includes a programmable converter controller which is adapted to reversibly configure the plurality of power stages.

Abstract: Computer with flexible operating system, referred to the FOS Computer, it is an invention of the electronic information field, aimed at creating a unique mechanism to run the computer. The FOS Computer abandons the graphical interface operating system that usually were fixed installed on the client computer, and replaced it with Flexible OS. The invention utilizes the sharing advantages of remote server, and an innovative computer hardware, jointly establishes a unique computer operational process. This process makes the computer more powerful, the application more flexible, the operation more secure and reliable. The key composition of the FOS Computer: A. Remote server based operating system, referred to as Server based OS B. Operating System Processing Unit, referred to as OSPU C. OSPU operating system, referred to as OSPU-OS. Among them, OSPU is an innovative computer component. OSPU is also the core hardware of the present invention.

Abstract: Disclosed is an electronic control unit capable of identifying an abnormality in a power supply voltage without narrowing the operating voltage range, and having minimal effects on cost and the circuit mounting surface area. The ECU includes a microcomputer containing an input terminal VCCin and an input terminal Vrin, a power supply IC that supplies a power supply voltage VCC to the input terminal VCCin, and as a reference-voltage-generator circuit a voltage-divider resistor and a voltage-divider resistor configuring a voltage-dividing circuit that outputs a sub-divided voltage Vc is sub-divided from the power supply voltage VCC, a capacitor coupled at one end to the input terminal Vrin and coupled on at the other end to ground, and a voltage isolation element coupled between the voltage-dividing circuit and the input terminal Vrin.

Abstract: An auxiliary power control system for enabling a software command that a management controller sends to the power supply to shut down auxiliary power. Such a power control system enables an AC cycle without needing to physically remove an AC power cord and provides additional power savings when a system is not in use. In certain embodiments, the auxiliary power control system includes a paradigm of a main power state, an auxiliary power state and a sub-auxiliary state. In this system many of the power states and wake vents apply to the auxiliary power state in addition to the main power state.

Abstract: An apparatus includes a distribution network that includes circuitry configured to receive first power from a first voltage source and second power from a second voltage source, and to deliver power to each of a plurality of electronic circuitry blocks (ECBs), including to deliver first ECB power to a first ECB and second ECB power to a second ECB. The first ECB power includes a first portion of the first power and a first portion of the second power. The apparatus also includes power management logic to dynamically adjust the power to be provided to each ECB. Responsive to a change in a first activity level of the first ECB, the power management logic is to change the first ECB power by adjustment of the first portion of the first power and adjustment of the first portion of the second power. Other embodiments are described and claimed.

Abstract: Systems, methods, and computer-readable media for upgrading electronic devices are provided. An exemplary method executed by a hardware processor may comprise providing a management agent on an electronic device for communicating with one or more device drivers associated with the electronic device. The management agent may be installed, for example, using a downloaded upgrade package. The method may further comprise upgrading the one or more device drivers to enable a direct connection between the management agent and the one or more device drivers. This direct connection, in some embodiments, may enable the management agent to access, using the one or more device drivers, persistent storage associated with the electronic device. The method may further comprise providing a new boot loader to the management agent, and overwriting, by the management agent, an existing boot loader in the persistent storage with the received new boot loader, using the one or more device drivers.

Abstract: A method of dynamically controlling power within a multicore CPU is disclosed and may include receiving a degree of parallelism in a workload of a zeroth core and determining whether the degree of parallelism in the workload of the zeroth core is equal to a first wake condition. Further, the method may include determining a time duration for which the first wake condition is met when the degree of parallelism in the workload of the zeroth core is equal to the first wake condition and determining whether the time duration is equal to a first confirm wake condition. The method may also include invoking an operating system to power up a first core when the time duration is equal to the first confirm wake condition.