Abstract: The present invention provides an organic EL panel and a manufacturing method of the organic EL layer which can slow the reduction in the light emission lifetime of an organic layer and allow a short-circuit defect to be repaired. Organic EL elements include: an organic EL element including a short-circuit portion, and an altered portion formed to be highly resistive by irradiating a cathode with a laser beam; and an organic EL element which does not include the short-circuit portion. In the organic EL element, an organic EL layer emits light when a voltage higher than or equal to a first voltage is applied. In the organic EL element, the organic EL layer emits light when a voltage higher than equal to a second voltage that is higher than the first voltage is applied.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and a display layer formed over the substrate and including a pixel area and a non-pixel area. The display also includes an upper thin layer formed over the display layer, wherein the upper thin layer comprises at least first and second conductive layers and a dielectric layer formed between the first and second conductive layers, wherein the second conductive layer is closer to the substrate than the first conductive layer, and wherein the first and second conductive layers are patterned as a touch electrode. The display further includes a light absorbing member at least partially overlapping the non-pixel area and not overlapping the pixel area.

Abstract: An optoelectronic device for detecting electromagnetic radiation includes a body of semiconductor material. A first region and a second region that form a junction are provided within the body. A recess extends into the body and is delimited by side arranged transverse to a main surface of the body. The junction is exposed by the sidewall to coupled electromagnetic radiation received in the recess into a photodiode formed by the junction.

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract: A semiconductor substrate is provided with a first cell region, the first cell region including: an n-type emitter region; a p-type first top body region; an n-type first barrier region; an n-type first pillar region; and a p-type first bottom body region, the semiconductor substrate may further comprise: an n-type drift region; a p-type collector region; an n-type cathode region, the n-type first barrier region may include a first peak position where a peak of the n-type impurity density is present within a part linked to the n-type first pillar region, and a second peak position where a peak of the n-type impurity density is present within a part in contact with the gate insulating layer, and a depth of the first peak position from a front surface of the semiconductor substrate is different from a depth of the second peak position from the front surface of the semiconductor substrate.

Abstract: The present application teaches, inter alia, methods and circuits for operating B-TRANs (double-base bidirectional bipolar junction transistors). Base drive circuits provide high-impedance drive to the base contact region on whichever side of the device is (instantaneously) operating as the collector. (B-TRANs, unlike other bipolar junction transistors, are controlled by applied voltage, not applied current.) Control signals operate preferred drive circuits, providing diode-mode turn-on and pre-turnoff operation, and a hard ON state with a low voltage drop (the “transistor-ON” state). In some (not necessarily all) preferred embodiments, a self-synchronizing rectifier circuit provides an adjustable low voltage for the gate drive circuit. Also, in some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while monitoring the base current at that terminal, so that no more base current than necessary is applied.

Abstract: A method of manufacturing an insulated gate bipolar transistor includes providing trenches extending from a first surface to a layer section in a semiconductor portion, introducing impurities into mesa sections between the trenches, and forming, from the introduced impurities, second portions of doped regions separated from source regions by body regions. The source regions are electrically connected to an emitter electrode. The second portions have a second mean net impurity concentration exceeding at least ten times a first mean net impurity concentration in first portions of the doped layer. The first portions extend from the body regions to the layer section, respectively.

Abstract: Methods, systems, circuits, and devices for power-packet-switching power converters using bidirectional bipolar transistors (BTRANs) for switching. Four-terminal three-layer BTRANs provide substantially identical operation in either direction with forward voltages of less than a diode drop. BTRANs are fully symmetric merged double-base bidirectional bipolar opposite-faced devices which operate under conditions of high non-equilibrium carrier concentration, and which can have surprising synergies when used as bidirectional switches for power-packet-switching power converters. BTRANs are driven into a state of high carrier concentration, making the on-state voltage drop very low.

Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Abstract: The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein.

Abstract: A quantum cascade laser manufacturing method includes: a step of pressing a mother stamper against a resin film having flexibility to make a resin stamper 201 having a second groove pattern P2; a step of making a wafer with an active layer formed on a semiconductor substrate; a step of forming a resist film 304 on a surface on the active layer side of the wafer; a step of pressing the resin stamper against the resist film 304 by air pressure to form a third groove pattern P3 on the resist film 304; and a step of etching the wafer with the resist film 304 serving as a mask to form a diffraction grating on a surface of the wafer.

Abstract: A light emitting diode chip includes a semiconductor layer sequence having an active layer that generates electromagnetic radiation, wherein the light emitting diode chip has a radiation exit area at a front side, the light emitting diode chip has a mirror layer at least in regions at a rear side situated opposite the radiation exit area, said mirror layer containing silver, a protective layer is arranged on the mirror layer, and the protective layer comprises a transparent conductive oxide.

Abstract: An organic light-emitting display device includes a first substrate and a second substrate that face each other; an organic light-emitting device that is disposed between the first and second substrates and includes a pixel electrode separately formed in each pixel, a common electrode facing the pixel electrode, and an organic light-emitting layer disposed between the pixel electrode and the common electrode; and an electrode unit and at least one wiring unit that are disposed between the first substrate and the second substrate, the electrode unit including at least one thin-film transistor for transmitting a light-emitting signal to the pixel electrode and at least one capacitor, wherein an optical property modification layer obtained by modifying an optical property of at least one of the electrode unit and the wiring unit is formed on a surface of the at least one of the electrode unit and the wiring unit.

Abstract: Methods for manufacturing a data storage device are provided. A method may include forming an interlayer dielectric layer on a substrate, patterning the interlayer dielectric layer in a peripheral region of the substrate to form first trenches, forming first bit lines in the first trenches, patterning the interlayer dielectric layer between the first bit lines in the peripheral region to form second trenches extending along the first trenches after the formation of the first bit lines, and forming second bit lines in the second trenches.

Abstract: A semiconductor device of an embodiment includes a p-type SiC impurity region containing a p-type impurity and an n-type impurity. Where the p-type impurity is an element A and the n-type impurity is an element D, the element A and the element D form a combination of Al (aluminum), Ga (gallium), or In (indium) and N (nitrogen), and/or a combination of B (boron) and P (phosphorus). The ratio of the concentration of the element D to the concentration of the element A in the above combination is higher than 0.33 but lower than 0.995, and the concentration of the element A forming part of the above combination is not lower than 1×1018 cm?3 and not higher than 1×1022 cm?3.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate including an isolation region between a first device region and a second device region. The isolation region includes a first portion adjacent the first device region and a second portion adjacent the second device region. The method includes selectively etching the second portion of the isolation region to a second height. The method forms an insulation layer over the first device region and second device region. The method further includes selectively etching the insulation layer over the first device region and the first portion of the isolation region. The first portion of the isolation region is etched to a first height substantially equal to the second height.

Abstract: A magnetic cell includes a free region between an intermediate oxide region (e.g., a tunnel barrier) and a secondary oxide region. Both oxide regions may be configured to induce magnetic anisotropy (“MA”) with the free region, enhancing the MA strength of the free region. A getter material proximate to the secondary oxide region is formulated and configured to remove oxygen from the secondary oxide region, reducing an oxygen concentration and an electrical resistance of the secondary oxide region. Thus, the secondary oxide region contributes only minimally to the electrical resistance of the cell core. Embodiments of the present disclosure therefore enable a high effective magnetoresistance, low resistance area product, and low programming voltage along with the enhanced MA strength. Methods of fabrication, memory arrays, memory systems, and electronic systems are also disclosed.

Abstract: A device with multiple encapsulated functional layers, includes a substrate, a first functional layer positioned above a top surface of the substrate, the functional layer including a first device portion, a first encapsulating layer encapsulating the first functional layer, a second functional layer positioned above the first encapsulating layer, the second functional layer including a second device portion, and a second encapsulating layer encapsulating the second functional layer.

Abstract: Aspects of the invention are directed to a single chip igniter such that it is possible to realize a reduction in operating voltage, an increase in noise tolerance, a reduction in size, and a reduction in cost. By reducing the gate threshold voltage of a MOS transistor, and reducing the operating voltages of a current limiter circuit, an overheat detector circuit, a timer circuit, an overvoltage protection circuit, an input hysteresis circuit, and the like, it is possible to reduce the operating voltage of a single chip igniter. In some aspects of the invention, the effective gate voltage of the MOS transistor is 1V or more, and the channel length of the MOS transistor is 4 ?m or less. Also, in some aspects of the invention, the thickness of a gate oxide film of the MOS transistor is 5 nm or more, 25 nm or less.

Abstract: The present application teaches, inter alia, methods and circuits for operating a B-TRAN (double-base bidirectional bipolar junction transistor). Exemplary base drive circuits provide high-impedance drive to the base contact region on the side of the device instantaneously operating as the collector. (The B-TRAN is controlled by applied voltage rather than applied current.) Current signals operate preferred implementations of drive circuits to provide diode-mode turn-on and pre-turnoff operation, as well as a hard ON state with low voltage drop (the “transistor-ON” state). In some preferred embodiments, self-synchronizing rectifier circuits provide adjustable low voltage for gate drive circuits. In some preferred embodiments, the base drive voltage used to drive the c-base region (on the collector side) is varied while base current at that terminal is monitored, so no more base current than necessary is applied. This solves the difficult challenge of optimizing base drive in a B-TRAN.