Abstract: A sensor element array and method of fabricating the same are provided. The sensor element array is disposed on a substrate and includes a first patterned conductive layer, a channel layer, a first insulation layer, a second patterned conductive layer, a second insulation layer, and a third patterned conductive layer. The first patterned conductive layer includes a sensing line, a first power line, a source/drain pattern and a branch pattern. The channel layer includes a first channel and a second channel. Margins of the first insulation layer and the second patterned conductive layer are substantially overlapped. The second patterned conductive layer includes a selecting line, a gate pattern, and a gate connecting pattern. The second insulation layer has a first connecting opening for exposing the gate connecting pattern. The third patterned conductive layer includes a sensing electrode electrically connected to the gate connecting pattern.

Abstract: An SRAM cell includes a first PMOS pass transistor comprising a first gate electrode disposed on a first PMOS active region, a first NMOS pass transistor comprising a second gate electrode disposed on a first NMOS active region, a first PMOS pull-up transistor and a first NMOS pull-down transistor sharing a third gate electrode disposed on the first PMOS active region and the first NMOS active region and extending therebetween, a second PMOS pass transistor comprising a fourth gate electrode disposed on a second PMOS active region, a second NMOS pass transistor comprising a fifth gate electrode disposed on a second NMOS active region and a second pull-up transistor and a second pull-down transistor sharing a sixth gate electrode disposed on the second PMOS active region and the second NMOS active region and extending therebetween.

Abstract: Solid state lighting (“SSL”) devices with cellular arrays and associated methods of manufacturing are disclosed herein. In one embodiment, a light emitting diode includes a semiconductor material having a first surface and a second surface opposite the first surface. The semiconductor material has an aperture extending into the semiconductor material from the first surface. The light emitting diode also includes an active region in direct contact with the semiconductor material, and at least a portion of the active region is in the aperture of the semiconductor material.

Abstract: A semiconductor device having a plurality of transistors includes a termination area that features a transistor with an asymmetric gate.

Abstract: A MEMS device having a device cavity in a substrate has a cavity etch monitor proximate to the device cavity. An overlying layer including dielectric material is formed over the substrate. A monitor scale is formed in or on the overlying layer. Access holes are etched through the overlying layer and a cavity etch process forms the device cavity and a monitor cavity. The monitor scale is located over a lateral edge of the monitor cavity. The cavity etch monitor includes the monitor scale and monitor cavity, which allows visual measurement of a lateral width of the monitor cavity; the lateral dimensions of the monitor cavity being related to lateral dimensions of the device cavity.

Abstract: A first test structure includes a first isolation region, a first gate electrode over the first isolation region, a first and a second semiconductor fin, and a first contact plug over the first and the second semiconductor fins. A second test structure includes a second isolation region, a second gate electrode over the second isolation region, a third semiconductor fin and a dielectric fin, and a second contact plug over the third semiconductor fin. The first, the second, and the third semiconductor fins and the dielectric fin have substantially a same fin height. A method includes measuring a first capacitance between the first gate electrode and the first contact plug, measuring a second capacitance between the second gate electrode and the second contact plug, and calculating the same fin height from a capacitance difference between the second capacitance and the first capacitance.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. A dummy pattern is formed between a fuse pattern and a semiconductor substrate so as to prevent the semiconductor substrate from being damaged, and a buffer pattern is formed between the dummy pattern and the semiconductor substrate, so that a dummy metal pattern primarily absorbs or reflects laser energy transferred to the semiconductor substrate during the blowing of the fuse pattern, and the buffer pattern secondarily reduces stress generated between the dummy pattern and the semiconductor substrate, resulting in the prevention of a defect such as a crack.

Abstract: An optical emitter includes a Light-Emitting Diode (LED) on a package wafer, transparent insulators, and one or more transparent electrical connectors between the LED die and one or more contact pads on the packaging wafer. The transparent insulators are deposited on the package wafer with LED dies attached using a lithography or a screen printing method. The transparent electrical connectors are deposited using physical vapor deposition, chemical vapor deposition, spin coating, spray coating, or screen printing and may be patterned using a lithography process and etching.

Abstract: A device includes a substrate having a first surface. A piezoelectric nanowire is disposed on the first surface of the substrate. The piezoelectric nanowire has a first end and an opposite second end. The piezoelectric nanowire is subjected to an amount of strain. A first Schottky contact is in electrical communication with the first end of the piezoelectric nanowire. A second Schottky contact is in electrical communication with the second end of the piezoelectric nanowire. A bias voltage source is configured to impart a bias voltage between the first Schottky contact and the second Schottky contact. A mechanism is configured to measure current flowing through the piezoelectric nanowire. The amount of strain is selected so that a predetermined current will flow through the piezoelectric nanowire when light of a selected intensity is applied to a first location on the piezoelectric nanowire.

Abstract: A semiconducting device includes a piezoelectric structure that has a first end and an opposite second end. A first conductor is in electrical communication with the first end and a second conductor is in electrical communication with the second end so as to form an interface therebetween. A force applying structure is configured to maintain an amount of strain in the piezoelectric member sufficient to generate a desired electrical characteristic in the semiconducting device.

Abstract: The present invention discloses a manufacturing method of vertical cavity surface emitting laser. The method includes following steps: providing a substrate; forming an epitaxial layer stack including an aluminum-rich layer; forming an ion-doping mask including a ring-shaped opening; doping ions in the epitaxial layer stack through the ring-shaped opening and forming a ring-shaped ion-doped region over the aluminum-rich layer; forming an etching mask on the ion-doping mask for covering the ring-shaped opening of the ion-doping mask; etching the epitaxial layer stack through the etching mask and ion-doping mask for forming an island platform; oxidizing the aluminum-rich layer for forming a ring-shaped oxidized region. In addition, the present invention also discloses a vertical cavity surface emitting laser manufactured by the above mentioned method.