Abstract: Electronic power modules are disclosed. In one example, an electronic power module includes a first aluminum substrate, a second aluminum substrate, and a third aluminum substrate arranged in a common plane. The electronic power module includes first gap separating the first aluminum substrate from the second aluminum substrate. The electronic power module includes a second gap separating the second aluminum substrate from the third aluminum substrate. The electronic power module includes a first semiconductor switching component electrically coupled to the first aluminum substrate and the second aluminum substrate. The electronic power module includes a second semiconductor switching component electrically coupled to the second aluminum substrate and the third aluminum substrate.

Abstract: The present disclosure provides a die assembly. The die assembly includes a first die, a second die and a third die stacked together. The first die includes a plurality of first metal lines facing a plurality of second metal lines of the second die, and a second substrate beneath the second metal lines faces a plurality of third metal lines of the third die. The die assembly further includes at least one first plug, a first redistribution layer and a second redistribution layer. The first plug penetrates through the second substrate to connect to at least one of the second metal lines. A first redistribution layer physically connects at least one of the first metal lines to at least one of the second metal lines, and a second redistribution layer physically connects at least one of the third metal lines to the first plug.

Abstract: The light source device includes a substrate, a light emitting unit mounted on the substrate, a frame disposed on the substrate, a metal shield fixed to an inner side of the frame and electrically coupled to the substrate, a light permeable member disposed on the frame, a cover plate disposed on the light permeable member and fixed to the frame, a detection unit electrically coupled to the substrate, and an uplift block that provides for the substrate to be disposed thereon.

Abstract: Technologies relating to implementing memristor crossbar arrays using non-filamentary RRAM cells are disclosed. In some implementations, an apparatus comprises: a first row wire; a first column wire; a non-filamentary RRAM; and an access control device. The non-filamentary RRAM and the access control device are serially connected; the non-filamentary RRAM and the access control device connect the first row wire with the first column wire. The non-filamentary RRAM and the access control device may form a cross-point device. The cross-point device may be less than 40×40 nm2. A set current of the non-filamentary RRAM may be no more than 10 ?A; and a reset current of the non-filamentary RRAM is no more than 10 ?A. The access control device may comprise a transistor or a selector.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: A semiconductor device includes a first conductive plate, a second conductive plate, first switching elements, second switching elements, a first supply terminal and a second supply terminal. The first and second conductive plates are spaced apart from each other in a first direction. The first switching elements are bonded to the first conductive plate, and are electrically connected to the second conductive plate. The second switching elements are bonded to the second conductive plate. The first supply terminal is bonded to the first conductive plate. The second supply terminal has a region that overlaps with the first supply terminal as viewed in a plan view. The second supply terminal is spaced apart from the first conductive plate and the first supply terminal in a thickness direction perpendicular to the first direction. The second supply terminal is electrically connected to the second switching elements.

Abstract: A semiconductor package includes a semiconductor chip and a polydimethylsiloxane (PDMS) layer that is provided on the semiconductor chip and of which upper surface is exposed to the outside. Since the semiconductor package may include the PDMS layer, heat emitting performance of the semiconductor package in a vacuum state may improve.

Abstract: A thermal management system includes an integrated circuit having an active side including a control circuit and a backside including a first set of electrodes distributed across the backside. The thermal management system includes a heat exchanger having a surface including a second set of electrodes. The thermal management system includes a thermal interface material including thermally conductive particles suspended in a fluid. The thermal interface material is disposed between the backside of the integrated circuit and the surface of the heat exchanger. The control circuit is configured to apply an electric field to the thermal interface material using a first electrode of the first set of electrodes and a second electrode of the second set of electrodes to excite at least some of the thermally conductive particles between the first electrode and the second electrode.

Abstract: A display apparatus is provided by the present invention, the display apparatus includes a first thin film transistor (TFT) disposed in a first pixel region and including a first semiconductor layer and a first gate electrode, where the semiconductor layer includes first source and drain regions; a second TFT disposed in a second pixel region adjacent the first pixel region and including a second semiconductor layer and a second gate electrode, where the second semiconductor layer includes a second source and drain regions; a first pixel electrode disposed in the first pixel region and including a first region where a first light-emitting layer is disposed and a second region extending from the first region and disposed on a first via hole; and a second pixel electrode disposed in the second pixel region and including a third region where a second light-emitting layer is disposed and a fourth region extending from the third region and disposed on a second via hole.

Abstract: A semiconductor module includes an insulation circuit substrate in which circuit patterns are formed on an upper surface of an insulation plate, switching elements that are arranged on an upper surface of the circuit patterns, a first heat dissipation plate that is arranged on a lower surface of the insulation plate, a casing member that surrounds a periphery of the insulation circuit substrate, the switching elements, and the first heat dissipation plate such that a lower surface of the first heat dissipation plate is exposed, and a second heat dissipation plate that is arranged on an upper surface side of the switching elements such that a prescribed gap is provided. The casing member has notch portions having a depth corresponding to a thickness of the second heat dissipation plate. At least a portion of the second heat dissipation plate engages with the notch portions.

Abstract: An integrated circuit (IC) package is described. The IC package includes a laminate substrate. The IC package also includes an active die on a surface of the laminate substrate. The IC package further includes fin-based thermal surface mount devices on the surface of the laminate substrate proximate the active die to provide an additional heat dissipation path.

Abstract: A semiconductor package includes a substrate, an electronic component mounted on an upper surface of the substrate so that a lower surface of the electronic component faces the upper surface of the substrate, a heat slug disposed on an upper surface of the electronic component so that a lower surface of the heat slug faces the upper surface of the electronic component, a bonding material bonding the heat slug to the upper surface of the electronic component, and an encapsulant in which the heat slug and the electronic component are embedded. A side surface of the heat slug extending between an edge of the lower surface of the heat slug and an edge of an upper surface of the heat slug forms a recess with the upper surface of the electronic component.

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Abstract: A semiconductor assembly is provided, that includes a semiconductor chip including an upper surface electrode and a lower surface electrode opposite to the upper surface electrode, a metallic wiring plate electrically connected to the semiconductor chip, and a soldering portion that bonds the upper surface electrode of the semiconductor chip to the metallic wiring plate by soldering, the semiconductor chip including a temperature detection portion, an anode wire for the temperature detection portion, and a first insulation layer that blocks the soldering portion and insulates the soldering portion from the anode wire.

Abstract: The invention relates to an optoelectronic semiconductor component (10) comprising a substrate (1), a first insulator layer (2), and a second insulator layer (3). Furthermore, the semiconductor component (10) comprises an organic semiconductor layer sequence (4) having an active area (4a) which, during operation, generates or receives light, a first electrode (5) and a second electrode (6), and encapsulation (7) which covers the organic semiconductor layer sequence (4) and the first insulator layer (2) completely and covers the second insulator layer (3) and the first electrode (5) or the second electrode (6) partially. Here, the first electrode (5) is arranged between the organic semiconductor layer sequence (4) and the first insulator layer (2), and the second electrode (6) is arranged on the organic semiconductor layer sequence (4), wherein the first electrode (5) and/or the second electrode (6) is/are at least partly arranged on the second insulator layer (3).

Abstract: Packaged electronic devices and integrated circuits include a ceramic material or other thermally conductive, electrically insulating substrate with a patterned electrically conductive feature on a first side, and an electrically conductive layer on a second side. The IC further includes a semiconductor die mounted to the substrate, the semiconductor die including an electrically conductive contact structure, and an electronic component, with an electrically insulating lamination structure enclosing the semiconductor die, the frame and the thermal transfer structure. A redistribution layer with a conductive structure is electrically connected to the electrically conductive contact structure.

Abstract: Methods of depositing a carbon film are discussed. Some embodiments selectively deposit a carbon film on a metal surface over a dielectric surface. Some embodiments form carbon pillars on metal surfaces selectively over dielectric surfaces. Some embodiments utilize carbon pillars in forming self-aligned vias.

Abstract: The present disclosure relates to a switching semiconductor device and a cooling apparatus thereof. The cooling apparatus of the switching semiconductor device of the present disclosure comprises a first heat dissipation plate configured to facilitate heat dissipation of a surface of the semiconductor device at an installation space, and a second heat dissipation plate disposed inside the installation space along a thickness direction of the first heat dissipation plate. The installation space is formed in a predetermined size at the surface of the semiconductor device, and the second heat dissipation plate is configured to contact the first heat dissipation plate so as to allow heat exchange. Accordingly, a heat dissipation area may be increased without increasing a size of the installation space.

Abstract: A semiconductor device includes a semiconductor die having a first surface and a second surface opposite to the first surface, a plurality of first real conductive pillars in a first region on the first surface, and a plurality of supporters in a second region adjacent to the first region. An area density of the plurality of supporters in the second region is in a range of from about 50% to about 100% to an area density of the plurality of first real conductive pillars in the first region. A method for manufacturing a semiconductor package including the semiconductor device is also disclosed in the present disclosure.