Patents Examined by Peniel M Gumedzoe
  • Semiconductor device
    Patent number: 11322425
    Abstract: Provided is a semiconductor device having excellent heat radiation performance and electromagnetic wave suppression effect. A semiconductor device 1 comprises: a semiconductor element 30 formed on a substrate 50; a conductive shield can 20 having an opening hole 21; a conductive cooling member 40 located above the conductive shield can 20; a heat conductive sheet 10 formed between the semiconductor element 30 and the conductive cooling member 40 at least through the opening hole 21; and a conductive member 11 electrically connecting the conductive shield can 20 and the conductive cooling member 40.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 3, 2022
    Assignee: Dexerials Corporation
    Inventor: Tatsuo Kumura
  • Electronic device
    Patent number: 11315889
    Abstract: Provided is an electronic device capable of simultaneously achieving heat dissipation, electromagnetic wave suppression effect and ESD protection at a high level.
    Type: Grant
    Filed: June 18, 2019
    Date of Patent: April 26, 2022
    Assignee: DEXERIALS CORPORATION
    Inventors: Yusuke Kubo, Sergey Bolotov
  • Semiconductor package having stiffener
    Patent number: 11315849
    Abstract: A semiconductor package includes a substrate including an upper surface and a side surface, an adhesive layer disposed on an edge of the upper surface of the substrate, and a stiffener including a horizontal portion disposed on the adhesive layer and extending in an horizontal direction to an outside of the substrate in a plan view and a vertical portion connected to the horizontal portion and extending vertically downwards from the horizontal portion. The vertical portion is spaced apart from the side surface of the substrate with a vertical gap extending in a vertical direction therebetween, and the outer width of the stiffener is 40 mm or more.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Suchang Lee, Dongok Kwak
  • External connection part of semiconductor module, semiconductor module, external connection terminal, and manufacturing method of external connection terminal of semiconductor module
    Patent number: 11315867
    Abstract: An external connection terminal of a semiconductor module is provided. The external connection terminal includes a conductor having an upper surface and a lower surface; a plated layer configured to cover the upper surface of the conductor; and a nut provided on the lower surface-side of the conductor for receiving a screw penetrating the conductor. The plated layer includes a low contact resistance region overlapping a region in which the nut is provided, and a high contact resistance region that is a region except the low contact resistance region, as seen from above, and the plated layer includes a convex portion and a concave portion on a surface in the high contact resistance region.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: April 26, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano
  • Electronic device with reduced non-device edge area
    Patent number: 11309522
    Abstract: A first product may be provided that comprises a substrate having a first surface, a first side, and a first edge where the first surface meets the first side; and a device disposed over the substrate, the device having a second side, where at least a first portion of the second side is disposed within 3 mm from the first edge of the substrate. The first product may further comprise a first barrier film that covers at least a portion of the first edge of the substrate, at least a portion of the first side of the substrate, and at least the first portion of the second side of the device.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: April 19, 2022
    Assignees: UNIVERSAL DISPLAY CORPORATION, THE TRUSTEES OF PRINCETON UNIVERSITY
    Inventors: Prashant Mandlik, Ruiqing Ma, Jeffrey Silvernail, Julia J. Brown, Lin Han, Sigurd Wagner, Luke Walski
  • Package structure for semiconductor device, and semiconductor device
    Patent number: 11309439
    Abstract: A package structure comprises a metal plate (20) where a slot is formed, a ceramic piece (60), and a metal heat sink (70) welded onto the back surface of the ceramic piece (60). The ceramic piece (60) and the metal heat sink (70) are vertically inserted into the slot and welded to the metal plate (20). A semiconductor and a matching circuit may be disposed on the metal heat sink (70). The ceramic piece (60) replaces a glass seal; metalized interconnection is provided inside the ceramic piece (60) for fabricating a metalized pattern having complex connection relations, and the electrical interconnection is more flexible. In the package structure, metalized wiring is carried out by using the ceramic piece. Compared with round lead machining, higher precision is achieved.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: April 19, 2022
    Assignee: He Bei Sinopack Electronic Tech Co., Ltd.
    Inventors: Yao Liu, Jun Li, Jing Zhao, Jing Sun, Bin Liang, Lin Feng Zhou, Di Gao
  • Circuit board and method for manufacturing the same
    Patent number: 11302620
    Abstract: A circuit board includes a board, first connection pads disposed on the board and arranged in a first direction, second connection pads disposed on the board and arranged in the first direction, a driving chip disposed on the board and between the first connection pads and the second connection pads, and a first adhesive layer disposed on the board and overlapping with an entirety of the first connection pads in a plan view. The second connection pads are spaced apart from the first connection pads in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: April 12, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Joo-Nyung Jang
  • Package assembly and method for manufacturing the same, package assembly of buck converter
    Patent number: 11302595
    Abstract: A package assembly can include: a die electrically connected to outer pins of the package assembly; an electronic component located above the die and electrically connected to the die, wherein the electronic component is connected to the outer pins of the package assembly through conductive pillars; and a heat dissipation structure located between the die and the electronic component to facilitate heat dissipation of the electronic component, where the heat dissipation structure physically isolates the die and the electronic component such that electromagnetic interference from the electronic component to the die is substantially prevented.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 12, 2022
    Assignee: Hefei Silergy Semiconductor Technology Co., Ltd.
    Inventors: Ke Dai, Jian Wei, Jiajia Yan
  • Microelectronic component having molded regions with through-mold vias
    Patent number: 11302643
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic component may include a substrate having a first face and an opposing second face, wherein the substrate includes a through-substrate via (TSV); a first mold material region at the first face, wherein the first mold material region includes a first through-mold via (TMV) conductively coupled to the TSV; and a second mold material region at the second face, wherein the second mold material region includes a second TMV conductively coupled to the TSV.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: April 12, 2022
    Inventors: Sanka Ganesan, Ram Viswanath, Xavier Francois Brun, Tarek A. Ibrahim, Jason M. Gamba, Manish Dubey, Robert Alan May
  • High-frequency module
    Patent number: 11302606
    Abstract: A high-frequency module 1a includes: a circuit board 2; a first component 3a, which has characteristics likely to be changed by heat, and a second component 3b, which generates heat, that are mounted on an upper surface 20a of the circuit board 2; a sealing resin layer 4 configured to cover each of the components 3a and 3b and a component 3c; a shield film 5 configured to cover a surface of the sealing resin layer 4; and a heat dissipation member 6 disposed above an upper surface 4a of the sealing resin layer 4. A recessed portion 11 is formed in the upper surface 4a of the sealing resin layer 4 as viewed in a direction perpendicular to the upper surface 20a of the circuit board 2. The recessed portion 11 can prevent the heat generated from the second component 3b from affecting the first component 3a.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: April 12, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshihito Otsubo, Shota Sato
  • Electronic device
    Patent number: 11302623
    Abstract: An electronic device includes a first metal plate including a first wiring and a second wiring, an electronic component mounted on a lower surface of the first wiring so as to overlap the second wiring in plan view, a second metal plate including an electrode electrically connected to the lower surface of the first wiring, and an insulation layer filling a space between the first metal plate, the second metal plate, and the electronic component and covering the electronic component. The upper surface of the second wiring is exposed from the insulation layer.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 12, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki Matsumoto, Tsukasa Nakanishi, Tadaaki Katsuyama
  • IGBT module with heat dissipation structure and method for manufacturing the same
    Patent number: 11302601
    Abstract: An IGBT module with a heat dissipation structure and a method for manufacturing the same are provided. The IGBT module with a heat dissipation structure includes a layer of IGBT chips, a bonding layer, a thick copper layer, a thermally-conductive and electrically-insulating layer, and a heat dissipation layer. A portion of the thermally-conductive and electrically-insulating layer is made of a polymer composite material, and a remaining portion of the thermally-conductive and electrically-insulating layer is made of a ceramic material. The thick copper layer is bonded onto the thermally-conductive and electrically-insulating layer by hot pressing. A fillet is formed at a bottom edge of the thick copper layer, and the bottom edge of the thick copper layer is embedded into the thermally-conductive and electrically-insulating layer.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 12, 2022
    Assignee: AMULAIRE THERMAL TECHNOLOGY, INC.
    Inventors: Tzu-Hsuan Wang, Tze-Yang Yeh, Chih-Hung Shih
  • Semiconductor device
    Patent number: 11289408
    Abstract: A semiconductor device according to one embodiment includes a first leadframe, a second leadframe, a semiconductor chip, and a conductive member. The second leadframe has a first face provided with a recess and is separated from the first leadframe. The semiconductor chip is mounted on the first leadframe. The conductive member has a second face connected to the first face with a conductive adhesive, the second face provided with a protrusion housed in the recess at least partially, and the conductive member electrically connected the semiconductor chip and the second leadframe to each other. The recess and the protrusion are longer in a first direction in which the first face extends than in a second direction along the first face and orthogonal to the first direction.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: March 29, 2022
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Kakeru Yamaguchi, Jun Karasawa
  • Semiconductor device
    Patent number: 11289405
    Abstract: There is provided a semiconductor device that includes a wiring layer having a main surface and a rear surface which face opposite sides in a thickness direction, a first insulating layer covering an entirety of the rear surface, a second insulating layer which is in contact with the main surface, a semiconductor element which faces the second insulating layer and is mounted on the wiring layer, and a sealing resin which is in contact with the second insulating layer and covers the semiconductor element, wherein surface roughness of the main surface is larger than surface roughness of the rear surface.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 29, 2022
    Assignee: ROHM Co., Ltd.
    Inventors: Satoshi Kageyama, Yoshihisa Takada
  • Electronic component and method of manufacturing electronic component
    Patent number: 11282771
    Abstract: An electronic component includes a metal member, an inductor, and a encapsulating resin. The metal member has an outer lead, an inner lead provided at a position opposed to the outer lead, and a post connecting the outer lead with the inner lead. The inductor is provided between the outer lead and the inner lead and connected to the outer lead or the inner lead. The encapsulating resin encapsulates the metal member and the inductor.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 22, 2022
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takayuki Matsumoto, Tsukasa Nakanishi, Tadaaki Katsuyama
  • Device, semiconductor package and method of manufacturing semiconductor package
    Patent number: 11282803
    Abstract: A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
    Type: Grant
    Filed: November 29, 2020
    Date of Patent: March 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Hao Tsai, Po-Yao Lin, Shin-Puu Jeng
  • Semiconductor package structure and electronic device
    Patent number: 11282767
    Abstract: A semiconductor package structure includes a package substrate and a semiconductor die. The package substrate includes a plurality of hollow vias extending through the package substrate. The semiconductor die is electrically connected to the package substrate. The hollow vias are disposed under the semiconductor die.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: March 22, 2022
    Assignee: ADVANCED SEMICONDUTOR ENGINEERING, INC.
    Inventors: Hsin-En Chen, Ian Hu, Jung-Che Tsai
  • Heat distribution device with flow channels
    Patent number: 11270925
    Abstract: A heat distribution device includes a main body, a recessed cavity and a plurality of ribs. The a recessed cavity is positioned within the main body and includes an interior surface, a peripheral wall extending around and defining the interior surface, and a central point within the recessed cavity. A plurality of ribs extend away from the interior surface of the recessed cavity. The plurality of ribs are concentrically arranged around the central point and define a plurality of channels therebetween. Each of the plurality of ribs have a top surface sloping toward the central point. The plurality of ribs are arranged so that the top surfaces of the plurality of ribs collectively form a non-planar surface within the heat distribution device.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 8, 2022
    Assignee: Google LLC
    Inventor: Xu Zuo
  • Direct write, high conductivity MMIC attach
    Patent number: 11264299
    Abstract: An integrated circuit assembly including an integrated circuit formed on one side of a substrate and a thermal spreading layer composed of a silver ink directly printed on an opposite side of the substrate from the integrated circuit, where the thermal spreading layer removes heat generated by the integrated circuit. The assembly also includes a heat sink thermally attached to the thermal spreading layer opposite to the substrate, where the heat sink is attached to the thermal spreading layer by printing the same material on the heat sink as the thermal spreading layer and pressing the spreading layer to the heat sink.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: March 1, 2022
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Jesse Tice, Steven J. Mass, Michael T. Barako
  • Solar array system and method of manufacturing
    Patent number: 11264522
    Abstract: A space-grade solar array includes relatively small cells with integrated wiring embedded into or incorporated directly onto a printed circuit board. The integrated wiring provides an interface for solar cells having back side electrical contacts. The single side contacts enable the use of pick and place (PnP) technology in manufacturing the space-grade solar array. The solar cell is easily and efficiently packaged and electrically interconnected with other solar cells on a solar panel such as by using PnP process. The back side contacts are matched from a size and positioning standpoint to corresponding contacts on the printed circuit board.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: March 1, 2022
    Assignee: Sierra Space Corporation
    Inventors: Brian Anthony, Rodney Dobson, Matthew Johnson, Scott Christiansen, L. Eric Ruhl