Abstract: Embodiments include an electronics package and methods of forming such packages. In an embodiment, the electronics package comprises a first package substrate. In an embodiment, the first package substrate comprises, a die embedded in a mold layer, a thermal interface pad over a surface of the die, and a plurality of solder balls over the thermal interface pad. In an embodiment, the thermal interface pad and the solder balls are electrically isolated from circuitry of the electronics package. In an embodiment, the electronics package further comprises a second package substrate over the first package substrate.

Abstract: A semiconductor device includes: a first semiconductor integrated circuit including at least a first terminal and a second terminal; a first lead frame connected to the first terminal; a second lead frame connected to the second terminal; and a mold resin covering the first semiconductor integrated circuit. The mold resin further covers the first lead frame with a portion of the first lead frame being exposed. The mold resin further covers the second lead frame with a tip of the second lead frame opposite to the second terminal being exposed. The mold resin includes a recess, and the recess is opened to expose only the portion and the mold resin.

Abstract: Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.

Abstract: A source terminal and a gate terminal are connected to a wiring pattern of the first substrate. A diode is provided under a second substrate such that an anode is connected to a wiring pattern of the second substrate. A plate-like portion of the first electrode is provided between the switching element and the diode, and a linking section of the first electrode connects the plate-like portion and the wiring pattern of the first substrate. A second electrode being substantially columnar and connecting the wiring pattern of the first substrate and the wiring pattern of the second substrate is provided in an opposite side to the linking section with the switching element interposed. A thickness of the plate-like portion of the first electrode is less than or equal to a thickness of each of the wiring pattern of the first substrate and the wiring pattern of the second substrate.

Abstract: A semiconductor structure includes a substrate having a seal ring region and a circuit region; one or more dielectric layers disposed on the substrate; a connection structure disposed in the one or more dielectric layers in the seal ring region, wherein the connection structure includes a stack of metal layers and metal vias connecting the stack of metal layers; and a metal plug disposed between the substrate and the connection structure in the seal ring region, wherein the metal plug has a multi-step profile in a cross-sectional view.

Abstract: A semiconductor device according to the present embodiment includes a wiring substrate having a wiring layer. A first semiconductor chip is provided above the wiring substrate. A metallic wire connects the first semiconductor chip and the wiring substrate to each other. A silicon chip is provided above the first semiconductor chip and covers above the metallic wire. A resin layer seals the first semiconductor chip and the silicon chip, and the metallic wire. The silicon chip is insulated from the wiring substrate.

Abstract: A semiconductor device comprises a substrate, a semiconductor chip on the substrate, and first and second leads between the substrate and the semiconductor chip. The first and second leads extend from an edge of the substrate toward below the semiconductor chip along a first direction parallel to a top surface of the substrate. The first lead includes a first bump connector and a first segment. The second lead includes a second bump connector. The first bump connector is spaced apart in the first direction from the second bump connector. The first segment of the first lead is spaced apart in a second direction from the second bump connector. The second direction is parallel to the top surface of the substrate and perpendicular to the first direction. A thickness of the first segment of the first lead is less than that of the second bump connector.

Abstract: The disclosure describes a lid allowing for a liquid thermal interface material (TIM) in a lidded flip chip package. The lid includes a reservoir structure so that a liquid system can be formed in the lidded flip chip package, allowing for a liquid TIM in the gap between the lid and the flip chip. The reservoir structure comprises a seal ring, a connecting hole and a reservoir which is a tunnel for taking in a liquid material and releasing it again from and to the gap according to the change of the gap volume. The lid further includes an injection hole and a plug for filling and removing liquid into or from the gap and reservoir. The lid further includes a plurality of pins, which extrude downwards from the bottom surface of the lid so as to strongly bond with the substrate of the flip chip package through an adhesive.

Abstract: A memory sub-system can include multiple memory devices and a thermal cooling element. The thermal cooling element includes a bottom surface that is coupled to a top surface of each of the memory devices. Furthermore, the thermal cooling element further has a top surface that includes a protrusions that extend above the top surface of the thermal cooling element to dissipate heat that is generated from the memory devices.

Abstract: A semiconductor device includes an insulating circuit substrate including an insulating plate, a first metal layer formed on a top surface of the insulating plate, and a second metal layer formed on a bottom surface of the insulating plate, a heatsink on whose top surface the insulating circuit substrate is disposed; semiconductor elements disposed on the top surface of the first metal layer through a bonding material, and a case that encloses a perimeter of the insulating circuit substrate and the semiconductor elements. The first metal layer includes circuit patterns electrically connected to the semiconductor elements and an annular pattern formed to enclose the perimeter of the circuit patterns with a gap provided with respect to the circuit patterns. The second metal layer is disposed at a spot that surfaces the annular pattern. The housing is affixed to the annular pattern through an adhesive.

Abstract: A semiconductor component includes: a semiconductor device; an insulating molded portion configured to encapsulate the semiconductor device; a terminal connected to the semiconductor device, the terminal being configured to project out from the insulating molded portion; and a cooler mounted with the insulating molded portion such that the semiconductor device is cooled; wherein a recessed portion is formed in a surface of the cooler on which the insulating molded portion is mounted so as to extend from a position facing the terminal to a position at inner side of an end portion of the insulating molded portion.

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Abstract: Various embodiments of laminated planar bus structures that minimize electromagnetic interference (EMI) and parasitic inductance are described. In one embodiment, a laminated planar bus structure may include a plurality of stacked conductive layers and a plurality of stacked insulation layers. The plurality of stacked conductive layers may include positive and negative conductive layers, and conductive ground layers stacked as outer layers as to enclose vertically the positive and the negative conductive layers. In another embodiment, the laminated planar bus structure may include a middle ground layer stacked in between the positive and the negative conductive layers to provide additional reduction in electric field strength. A laminated planar bus structure that is integrated with other power electronics components is also presented.

Abstract: An organic light emitting diode (OLED) display including: a substrate; an organic light emitting diode formed on the substrate; a metal oxide layer formed on the substrate and covering the organic light emitting diode; a first inorganic layer formed on the substrate and covering the organic light emitting diode; a second inorganic layer formed on the first inorganic layer and contacting the first inorganic layer at an edge of the second inorganic layer; an organic layer formed on the second inorganic layer and covering a relatively smaller area than the second inorganic layer; and a third inorganic layer formed on the organic layer, covering a relatively larger area than the organic layer, and contacting the first inorganic layer and the second inorganic layer at an edge of the third inorganic layer.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

Abstract: A semiconductor device including a substrate, a semiconductor package, a plurality of pillars and a lid is provided. The semiconductor package is disposed on the substrate and includes at least one semiconductor die. The plurality of pillars are disposed on the semiconductor package. The lid is disposed on the substrate and covers the semiconductor package and the plurality of pillars. The lid includes an inflow channel and an outflow channel to allow a coolant to flow into and out of a space between the substrate, the semiconductor package, the plurality of pillars and the lid. An inner surface of the lid, which faces and overlaps the plurality of pillars along a stacking direction of the semiconductor package and the lid, is a flat surface.

Abstract: A method for producing a semiconductor device includes providing a carrier configured to carry at least one semiconductor chip on a first side, and dispensing a polymer onto a second side situated opposite the first side in order to produce a sealing ring. The polymer is dispensed in such a way that the sealing ring produced has different heights perpendicular to the second side along its circumference.

Abstract: Provided is a semiconductor device having excellent heat dissipation capacity and electromagnetic wave suppression effect. A semiconductor device 1 includes a semiconductor device 30; a tubular conductive shield can 20 provided to surround a side surface 30a of the semiconductor device 30; a conductive cooling member 40; and a conductive thermally conductive sheet 10 formed between the semiconductor device 30 and the cooling member 40. The conductive shield can 20 and the cooling member 40 are electrically connected through the conductive thermally conductive sheet 10 therebetween.

Abstract: The present disclosure provides a method for forming an integrated circuit (IC) structure. The method comprises providing a substrate including a conductive feature; forming aluminum (Al)-containing dielectric layer on the conductive feature; forming a low-k dielectric layer on the Al-containing dielectric layer; and etching the low-k dielectric layer to form a contact trench aligned with the conductive feature. A bottom of the contact trench is on a surface of the Al-containing dielectric layer.