Abstract: A semiconductor device package includes a semiconductor device, a conductive bump, a first encapsulant and a second encapsulant. The semiconductor device has a first surface, a second surface and a lateral surface. The second surface is opposite to the first surface. The lateral surface extends between the first surface and the second surface. The semiconductor device comprises a conductive pad adjacent to the first surface of the semiconductor device. The conductive bump is electrically connected to the conductive pad. The first encapsulant covers the first surface of the semiconductor device and a first portion of the lateral surface of the semiconductor device, and surrounds the conductive bump. The second encapsulant covers the second surface of the semiconductor device and a second portion of the lateral surface of the semiconductor device.

Abstract: A semiconductor device package includes a package substrate having a die attach region, a silicon carbide (SiC) substrate having a first surface including a semiconductor device layer thereon and a second surface that is opposite the first surface, and a die attach metal stack. The die attach metal stack includes a sputtered die attach material layer that attaches the second surface of the SiC substrate to the die attach region of the package substrate, where the sputtered die attach material layer comprises a void percent of about 15% or less. The sputtered die attach material layer may be formed using a sputter gas including at least one of krypton (Kr), xenon (Xe), or radon (Rn). The die attach metal stack may further include a metal interlayer that prevent contacts with a first barrier metal layer during a phase transition of the die attach material layer.

Abstract: A method includes placing metal-core solder balls on conductive pads of a first semiconductor device, wherein the metal-core solder balls include a metal core surrounded by a solder material, and forming a device structure, forming the device structure including placing the first semiconductor device on a carrier substrate, encapsulating the first semiconductor device with an encapsulant, wherein the encapsulant covers the metal-core solder balls, performing a planarization process on the encapsulant, wherein the planarization process exposes the metal-core solder balls, and forming a redistribution structure over the encapsulant and the first semiconductor device, wherein the redistribution structure is electrically connected to the metal-core solder balls.

Abstract: A low parasitic inductance power module, which includes an input power terminal, an output power terminal, a top metal insulating substrate, a bottom metal insulating substrate and a plastic package shell, wherein the input power terminal includes a positive power terminal and a negative power terminal, the top metal insulating substrate and the bottom metal insulating substrate are stacked, chips are sintered on faces of both the top metal insulating substrate and the bottom metal insulating substrate opposite to each other, and the positive power terminal, the negative power terminal, and the output power terminal are all electrically connected with the chips; and the output power terminal includes a welding portion and a connecting portion located outside the plastic package shell, and the welding portion is located between the top metal insulating substrate and the bottom metal insulating substrate.

Abstract: A semiconductor device includes: a semiconductor substrate; a first metal ring which is provided outside a periphery of a circuit region including a signal pad on one surface side of the semiconductor substrate and is interrupted by one or a plurality of openings; a second metal ring provided outside a periphery of the first metal ring; and a resistance layer that connects ends of the first metal ring interrupted by the one or the plurality of openings to each other, wherein the first metal ring includes a first wall portion and a second wall portion that sandwich the circuit region, and a third wall portion and a fourth wall portion that sandwich the circuit region and are connected to the first wall portion and the second wall portion, and the one or the plurality of openings is arranged in the first wall portion close to the signal pad.

Abstract: A semiconductor device includes a predetermined number of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin that covers the semiconductor element and a part of each lead. Each lead includes some portions exposed from the sealing resin. A surface plating layer is formed on at least one of the exposed portions of the respective leads.

Abstract: In a semiconductor device, a first outer edge of a conductive pattern is located between the outermost edge of a first dimple and the innermost edge of a second dimple in a cross-sectional view of the device. When thermal stress due to temperature changes in the semiconductor device is applied to the ceramic circuit board, the first and second dimples suppress deformation of the ceramic circuit board that is caused due to the temperature changes. As a result, cracks in the ceramic circuit board and separation of the metal plate and the conductive pattern are prevented.

Abstract: The present disclosure provides a semiconductor assembly and method of manufacturing the same. The semiconductor assembly includes a semiconductor device, a bulk semiconductor, a passivation layer, at least one conductive plug, a plurality of protective liners, and a plurality of isolation liners. The bulk semiconductor is disposed over the semiconductor device. The passivation layer covers the bulk semiconductor. The conductive plug comprises a first block disposed in the passivation layer and a second block disposed between the first block and the conductive pad, wherein portions of peripheries of the first and second blocks of the conductive plug are surrounded by the protective liners and the isolation liners.

Abstract: An integrated fan-out package including an integrated circuit, an insulating encapsulation, and a redistribution circuit structure is provided. The integrated circuit includes an active surface, a plurality of sidewalls connected to the active surface, and a plurality of pads distributed on the active surface. The insulating encapsulation encapsulates the active surface and the sidewalls of the integrated circuit. The insulating encapsulation includes a plurality of first contact openings and a plurality of through holes, and the pads are exposed by the first contact openings. The redistribution circuit structure includes a redistribution conductive layer, wherein the redistribution conductive layer is disposed on the insulating encapsulation and is distributed in the first contact openings and the through holes. The redistribution conductive layer is electrically connected to the pads through the first contact openings. A method of fabricating the integrated fan-out package is also provided.

Abstract: A Monolithic Microwave Integrated Circuit (MMIC) structure having a thermally conductive substrate; a semiconductor layer disposed on a first portion of an upper surface of the substrate; an active mesa-shaped semiconductor device layer disposed on the semiconductor layer; and a passive electrical device disposed directly on a second portion of the upper surface of the substrate.

Abstract: A busbar assembly according to the present invention includes a first busbar formed by a conductive metal flat plate; a second busbar formed by a conductive metal flat plate, the second busbar disposed in the same plane as the first busbar with a gap being provided between opposing side surfaces of the first and second busbars; and an insulating resin layer filled in the gap so as to mechanically connect the opposing side surfaces of the first and second busbars. Preferably, the opposing side surface of at least one of the first and second busbars is an inclined surface that is closer to the opposing side surface of the other of the first and second busbars from one side toward the other side in the thickness direction.

Abstract: A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.

Abstract: An IC is provided. The IC includes a plurality of P-type gate-all-around (GAA) field-effect transistors (FETs). At least one first P-type GAA FET includes a plurality of silicon (Si) channel regions vertically stacked over an N-type well region. At least one second P-type GAA FET includes a plurality of silicon germanium (SiGe) channel regions vertically stacked over the N-type well region.

Abstract: A semiconductor package includes a substrate, a plurality of electronic components mounted on a first surface of the substrate, and an encapsulant disposed on the first surface of the substrate so that at least one of the plurality of electronic components is embedded in the encapsulant. The substrate includes a flow preventing portion including at least one flow preventing groove disposed in the first surface and adjacent to the encapsulant and/or at least one dam disposed on the first surface and adjacent to the encapsulant.

Abstract: A stacked semiconductor package includes a first die, a second die stacked on a surface of the first die, a heat dissipation layer disposed on the surface, a heat insulation layer disposed on the surface to cover the heat dissipation layer and the first die, a heat sink disposed on the second die, and a heat conduction structure spaced apart from the second die in a lateral direction on the surface to connect the heat dissipation layer to the heat sink.

Abstract: A semiconductor package including: a first package; a second package on the first package, the second package including a second package substrate, first and second semiconductor chips on the second package substrate, and a second molding part on the second package substrate and covering the first and second semiconductor chips; and a fill part between the first package and the second package, a first through hole that penetrates the second package substrate, the first through hole being between the first and second semiconductor chips, a second through hole that penetrates the second molding part, the second through hole being connected to the first through hole, and wherein the fill part has an extension disposed in the first through hole and the second through hole.

Abstract: Embodiments of the disclosure provide a capacitor structure for an integrated circuit (IC), and methods to form the capacitor structure. The capacitor structure may include: a first ring electrode in an inter-level dielectric (ILD) layer on a substrate; an inner electrode positioned within the first ring electrode; and a capacitor dielectric separating the first ring electrode and the inner electrode, and separating a bottom surface of the inner electrode from the ILD layer.

Abstract: [Object] To make it possible to improve viewing angle characteristics more. [Solution] Provided is a display device including: a plurality of light emitting sections formed on a substrate. The light emitting section has a configuration in which a luminescence layer is sandwiched by a first electrode functioning as a reflecting electrode and a second electrode in a stacking direction, a surface of the first electrode facing the luminescence layer is inclined from a plane perpendicular to the stacking direction in at least a partial region in a display surface, and an inclination direction of the first electrode has a distribution in the display surface.

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include control gate regions and include second regions proximate to the control gate regions. High-k dielectric structures are directly against the control gate regions and extend entirely across the insulative levels. Charge-blocking material is adjacent to the high-k dielectric structures. Charge-storage material is adjacent to the charge-blocking material. The charge-storage material is configured as segments which are vertically stacked one atop another, and which are vertically spaced from one another. Gate-dielectric material is adjacent to the charge-storage material. Channel material extends vertically along the stack and is adjacent to the gate-dielectric material. Some embodiments include integrated assemblies, and methods of forming integrated assemblies.

Abstract: A process of forming a metal-insulator-metal (MIM) capacitor may be incorporated into a process of forming metal bond pads connected directly to a top metal interconnect layer (e.g., Cu MTOP). The MIM capacitor may include a dielectric layer formed between a bottom plate defined by the Cu MTOP and a top plate comprising an extension of, or connected directly to, a metal bond pad formed above the Cu MTOP. The process of forming the MIM capacitor may include etching an opening in a passivation layer formed over the Cu MTOP to expose a top surface of the Cu MTOP, forming a dielectric layer extending into the passivation layer opening and onto the exposed Cu MTOP surface, removing portions of the dielectric layer to define a capacitor dielectric, and depositing bond pad metal extending into the passivation layer opening and onto the capacitor dielectric, to define the MIM capacitor top plate.