Patents Examined by Peter Bradford
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Patent number: 11978808Abstract: Vertical etch heterolithic integrated circuit devices are described. A method of manufacturing NIP diodes is described in one example. A P-type substrate is provided, and an intrinsic layer is formed on the P-type substrate. An oxide layer is formed on the intrinsic layer, and one or more openings are formed in the oxide layer. One or more N-type regions are implanted in the intrinsic layer through the openings in the oxide layer. The N-type regions form cathodes of the NIP diodes. A dielectric layer deposited over the oxide layer is selectively etched away with the oxide layer to expose certain ranges of the intrinsic layer to define a geometry of the NIP diodes. The intrinsic layer and the P-type substrate are vertically etched away within the ranges to expose sidewalls of the intrinsic layer and the P-type substrate. The P-type substrate forms the anodes of the NIP diodes.Type: GrantFiled: May 2, 2022Date of Patent: May 7, 2024Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.Inventors: Timothy Edward Boles, James J. Brogle, Margaret Mary Barter, David Hoag, Michael G. Abbott
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Patent number: 11970772Abstract: Methods and apparatuses for controlling precursor flow in a semiconductor processing tool are disclosed. A method may include flowing gas through a gas line, opening an ampoule valve(s), before a dose step, to start a flow of precursor from the ampoule to a process chamber through the gas line, closing the ampoule valve(s) to stop the precursor from flowing out of the ampoule, opening a process chamber valve, at the beginning of the dose step, to allow the flow of precursor to enter the process chamber, and closing the process chamber valve, at the end of the dose step, to stop the flow of precursor from entering the process chamber. A controller may include at least one memory and at least one processor and the at least one memory may store instructions for controlling the at least one processor to control precursor flow in a semiconductor processing tool.Type: GrantFiled: October 20, 2021Date of Patent: April 30, 2024Assignee: Lam Research CorporationInventors: Purushottam Kumar, Adrien LaVoie, Jun Qian, Hu Kang, Ishtak Karim, Fung Suong Ou
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Patent number: 11968821Abstract: A two transistor-one capacitor memory cell comprises first and second transistors laterally displaced relative one another. A capacitor is above the first and second transistors. The capacitor comprises a conductive first capacitor node directly above and electrically coupled to a first node of the first transistor. A conductive second capacitor node is directly above the first and second transistors and is electrically coupled to a first node of the second transistor. A capacitor insulator is between the first and second capacitor nodes. The second capacitor node comprises an elevationally-extending conductive pillar directly above the first node of the second transistor. The conductive pillar has an elevationally outer portion that is of four-sided diamond shape in horizontal cross-section. Other memory cells, including arrays of memory cells are disclosed as are methods.Type: GrantFiled: November 16, 2021Date of Patent: April 23, 2024Assignee: Micron Technology, Inc.Inventor: Scott E. Sills
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Patent number: 11948836Abstract: Apparatuses and methods to provide electronic devices having metal films are provided. Some embodiments of the disclosure utilize a metallic tungsten layer as a liner that is filled with a metal film comprising cobalt. The metallic tungsten layer has good adhesion to the cobalt leading to enhanced cobalt gap-fill performance.Type: GrantFiled: October 11, 2021Date of Patent: April 2, 2024Assignee: Applied Materials, Inc.Inventors: Yu Lei, Sang-Hyeob Lee, Chris Pabelico, Yi Xu, Tae Hong Ha, Xianmin Tang, Jin Hee Park
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Patent number: 11943920Abstract: A semiconductor memory device includes a semiconductor substrate, a select gate on the semiconductor substrate, a control gate disposed adjacent to the select gate and having a first sidewall and a second sidewall, and a charge storage layer between the control gate and the semiconductor substrate. The control gate includes a third sidewall close to the second sidewall of the select gate, a fourth sidewall opposite to the third sidewall, and a non-planar top surface between the third sidewall and the fourth sidewall. The non-planar top surface includes a first surface region that descends from the third sidewall to the fourth sidewall. The charge storage layer extends to the second sidewall of the select gate.Type: GrantFiled: September 7, 2021Date of Patent: March 26, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Liang Yi, Zhiguo Li, Chi Ren, Xiaojuan Gao, Boon Keat Toh
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Patent number: 11943971Abstract: In a display device in which an OLED is formed by a separate coating method, improving the accuracy of vapor deposition position and reducing display defects are established. In the array substrate, a display unit that displays an image configured with a plurality of pixels is formed. A first convex portion and a second convex portion are provided on a surface of a boundary region between the pixels of the array substrate. A first organic layer including a layer exhibiting a first emission color is stacked on the pixel electrode of the pixel, and second organic layers including a layer exhibiting a second emission color are stacked on the pixel electrode of the pixels. The first organic layer is provided to cover only the first convex portion. The second organic layers are provided not to cover any one of the first convex portion and the second convex portion.Type: GrantFiled: May 3, 2021Date of Patent: March 26, 2024Assignee: Japan Display Inc.Inventor: Masamitsu Furuie
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Patent number: 11925060Abstract: A display apparatus includes a display panel having a first area and a second area, a main body supporting the display panel, an auxiliary member arranged in the main body, and a reflective member arranged between the auxiliary member and the display panel, wherein the reflective member may movably be provided to overlap the first area or the second area. Therefore, light emitted from the display panel toward the inside of the main body may be reflected in the outside, and a luminance difference between the first area and the second area of the display panel may be prevented from occurring, whereby a user's satisfaction for an image may be enhanced.Type: GrantFiled: December 27, 2020Date of Patent: March 5, 2024Assignee: LG DISPLAY CO., LTD.Inventors: MoonSoo Kim, Suhyeon Kim
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Patent number: 11923488Abstract: A light emitting device includes: a light emitting element having a top surface; and a light-transmissive member covering at least the top surface of the light emitting element, the light-transmissive member having a principal surface located above the top surface of the light emitting element. The principal surface of the light-transmissive member comprises a plurality of concave portions.Type: GrantFiled: June 18, 2021Date of Patent: March 5, 2024Assignee: NICHIA CORPORATIONInventors: Naoki Musashi, Takayoshi Wakaki
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Patent number: 11925069Abstract: A display device includes a substrate including an emission area and a non-emission area and in which a plurality of sub-pixels are defined, first electrodes disposed in the plurality of sub-pixels, respectively, a bank that is disposed in the non-emission area between the plurality of sub-pixels, and exposes the first electrode through an opening, a protrusion disposed in a second non-emission area of the non-emission area which is divided into a first non-emission area at a flat top surface of the bank and the second non-emission area at an inclined top surface of the bank, an organic layer disposed on the first electrodes, and a second electrode disposed on the organic layer.Type: GrantFiled: June 1, 2021Date of Patent: March 5, 2024Assignee: LG Display Co., Ltd.Inventors: ByoungHyun Koo, SungWook Yoon, Chung Hoon Lee, DongMin Jang
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Patent number: 11903260Abstract: The present disclosure provides a display panel, including a first pixel group, a second pixel group, and a third pixel group with different colors. The first pixel group and the second pixel group are sequentially arranged along a first direction, and both include four sub-pixels arranged in a matrix. The third pixel group is adjacent to the first pixel group and the second pixel group, and the third pixel group includes at least two third sub-pixels sequentially arranged along the first direction. A demand of products for printing accuracy requirement of a printing equipment can be reduced under a premise that a number of high pixels per inch (PPI) remains unchanged.Type: GrantFiled: June 3, 2020Date of Patent: February 13, 2024Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Yifei Bing
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Patent number: 11894297Abstract: Disclosed are metal-insulator-metal capacitors and integrated chips. In one embodiment, a metal-insulator-metal capacitor includes N electrodes and (N?1) passivation layers, wherein the N electrodes and the (N?1) passivation layers are alternately stacked on a substrate. N is an integer larger than 1. Thicknesses of the N electrodes gradually increase in a direction parallel to a normal direction of the substrate.Type: GrantFiled: July 29, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: I-Che Lee
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Patent number: 11894501Abstract: The present disclosure provides a lighting device and a manufacturing method thereof. The lighting device includes a substrate, a light emitting unit, a light adjusting layer and at least one electrode connecting element. The light emitting unit is disposed on the substrate and includes a light output surface and a plurality of top electrodes. The light adjusting layer is disposed on the light emitting unit, and the light adjusting layer includes a first portion and a second portion connected to the first portion. Wherein the top electrodes are electrically connected to each other through the electrode connecting element, the first portion only partially covers the light output surface, and the second portion does not cover the light output surface.Type: GrantFiled: October 30, 2022Date of Patent: February 6, 2024Assignee: InnoLux CorporationInventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
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Patent number: 11895858Abstract: A display device includes: light-emitting regions different in luminescent colors and including luminescent layers separated for each of the luminescent colors; a low-threshold layer lower in threshold voltage than any one of the luminescent layers included in a pair of different-color light-emitting regions included in the light-emitting regions, different in the luminescent colors, and adjacent to each other; a continuous layer under the luminescent layers and the low-threshold layer, including first areas and a second area continuously, the first areas being in contact with the respective light-emitting regions, the second area being in contact with the low-threshold layer; pixel electrodes under the continuous layer, overlapping with the respective light-emitting regions; and a counter electrode over the luminescent layers and the low-threshold layer, being opposed to the pixel electrodes. The low-threshold layer is between the pair of different-color light-emitting regions.Type: GrantFiled: September 22, 2021Date of Patent: February 6, 2024Assignee: Japan Display Inc.Inventor: Hayata Aoki
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Patent number: 11889739Abstract: The present invention provides an organic light-emitting diode (OLED) device and a manufacturing of the OLED device. The OLED device includes a light-emitting layer, an insulating layer, an electron transport layer, and an electron injection layer. The insulating layer is arranged on one side of the light-emitting layer, and a through hole is in the insulating layer. The through hole is arranged corresponding to a middle portion of the light-emitting layer. The electron transport layer is in a lower portion of the through hole and attached to a surface of the light-emitting layer. The electron injection layer is in an upper portion of the through hole and attached to one side of the electron transport layer away from the light-emitting layer.Type: GrantFiled: November 8, 2019Date of Patent: January 30, 2024Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventors: Feng Wei, Aiguo Tu
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Patent number: 11882735Abstract: A display apparatus includes a base substrate on which a display area and a non-display area are defined, a first via insulating layer on the base substrate, a first power supply wire in the non-display area on the first via insulating layer, a second power supply wire in the non-display area on the first via insulating layer spaced apart from the first power supply wire, a first dam on the base substrate, overlapping the first and second power supply wires, and extending along the non-display area, a first stacked structure on the first via insulating layer between the first dam and the display area, and having a height less than a height of the first dam, and an organic layer on the first stacked structure and the first dam to overlap a substantially entire portion of the first stacked structure and at least a portion of the first dam.Type: GrantFiled: December 8, 2020Date of Patent: January 23, 2024Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Ki Ho Bang, Eun Hye Kim, Won Suk Choi
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Patent number: 11871620Abstract: An OLED panel includes a plurality of light-emitting elements, that each light-emitting element includes a fence structure on a substrate and in an opening of a pixel definition layer. A trench is formed between the fence structure and the pixel definition layer. Charge transport layer is disconnected at the trench by a shadowing effect of the fence structure during thermal evaporation of the charge transport layer. Therefore, lateral current leakage between two adjacent light-emitting elements is minimized.Type: GrantFiled: May 27, 2021Date of Patent: January 9, 2024Assignee: SeeYa Optronics, Ltd.Inventor: Zhongshou Huang
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Patent number: 11864426Abstract: An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes: a base substrate; a light-emitting functional layer including a first light-emitting functional portion and a second light-emitting functional portion adjacent to each other; and a photo spacer (PS), the PS is located between the first light-emitting functional portion and the second light-emitting functional portion, the PS includes a plurality of protrusions protruded in a direction away from the base substrate and a first recess located between adjacent protrusions.Type: GrantFiled: May 14, 2019Date of Patent: January 2, 2024Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Chang Luo, Fengli Ji, Jianpeng Wu
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Patent number: 11864444Abstract: A light emitting display apparatus includes a substrate including a subpixel area having a non-light emission portion, a first light emission portion and a second light emission portion; a driving transistor disposed in the non-light emission portion; an overcoat layer disposed on the substrate to overlay the driving transistor; first and second anode electrodes disposed to be spaced apart from each other on the overcoat layer of each of the first light emission portion and the second light emission portion and commonly connected to the driving transistor; a self-light emitting device on the first anode electrode and the second anode electrode; and a second electrode on the self-light emitting device. The first light emission portion and the second light emission portion can have light extraction structures different from each other.Type: GrantFiled: December 15, 2020Date of Patent: January 2, 2024Assignee: LG DISPLAY CO., LTD.Inventors: Jihyang Jang, Jintae Kim
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Patent number: 11849599Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.Type: GrantFiled: December 18, 2020Date of Patent: December 19, 2023Assignee: Japan Display Inc.Inventor: Akinori Kamiya
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Patent number: 11848255Abstract: Disclosed are semiconductor package structure and semiconductor modules including the same. The semiconductor module includes a circuit board, a first semiconductor package over the circuit board, and a connection structure on the circuit board and connecting the circuit board and the first semiconductor package. The first semiconductor package includes a first package substrate. A difference in coefficient of thermal expansion between the connection structure and the circuit board may be less than a difference in coefficient of thermal expansion between the circuit board and the first package substrate.Type: GrantFiled: June 18, 2020Date of Patent: December 19, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: YoungJoon Lee, Sunwon Kang