Patents Examined by Peter Bradford
  • Patent number: 10840413
    Abstract: An optoelectronic device includes at least one optoelectronic semiconductor chip that emits radiation, at least one metallic reflecting surface, at least one functional component having a component surface different from the metallic reflecting surface, and a barrier layer stack for protection against corrosive gases arranged both on the at least one metallic reflecting surface and the component surface, wherein the barrier layer stack includes at least one inorganic oxide, oxynitride or nitride layer and at least one plasma-polymerized siloxane layer.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 17, 2020
    Assignee: OSRAM OLED GmbH
    Inventors: Thomas Reeswinkel, Richard Scheicher
  • Patent number: 10825919
    Abstract: A method of fabricating semiconductor devices is provided. The method includes forming a fin structure on a substrate, in which the fin structure includes a fin stack of alternating first and second semiconductor layers and forming recesses in the fin stack at source and drain regions. The method also includes etching the second semiconductor layers to form recessed second semiconductor layers, and forming third semiconductor layers on sidewalls of the recessed second semiconductor layers. The method further includes epitaxially growing source and drain structures in the recesses, removing the recessed second semiconductor layers to form spaces between the first semiconductor layers, and oxidizing the third semiconductor layers to form inner spacers. In addition, the method includes forming a gate structure to fill the spaces and to surround the first semiconductor layers.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chun-Hsiung Lin, Pei-Hsun Wang, Chih-Hao Wang, Kuo-Cheng Ching, Jui-Chien Huang
  • Patent number: 10797066
    Abstract: A memory device includes a substrate, a first memory structure including a plurality of first word lines stacked on the substrate in a direction perpendicular to a top surface of the substrate, an inter-metal layer on the first memory structure and including a plurality of intermediate pads connected with separate, respective first word lines of the plurality of first word lines, a second memory structure including a plurality of second word lines stacked on the inter-metal layer in the direction perpendicular to the top surface of the substrate, and an upper metal layer on the second memory structure and including a plurality of upper pads connected with separate, respective second word lines of the plurality of second word lines.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: October 6, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-Yeol Lee, Chanho Kim
  • Patent number: 10790473
    Abstract: The disclosure relates to a high-aperture-ratio microdisplay with a microcavity structure. The microdisplay comprises a substrate, unit pixels, driving elements, and organic light-emitting diodes. The organic light-emitting diodes each comprise: an anode, an organic emission layer, and a cathode. The anode is formed by sequentially stacking a reflecting electrode, a first dielectric layer, a second dielectric layer, and a transparent electrode. The organic emission layer is stacked over the anode. The cathode is stacked over the organic emission layer. The first dielectric layer and the second dielectric layer have contact portion that open at least one corner of the reflecting electrode. The anode is connected to the reflecting electrode through the contact portions.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: September 29, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Jiyeon Park, Hansun Park, Hyungseok Bang, Hyeongjun Lim
  • Patent number: 10777501
    Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: September 15, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shingo Nakajima, Ryota Asada, Hidenobu Nagashima, Masayuki Akou
  • Patent number: 10756143
    Abstract: A transparent display panel and a transparent display device including the same, including a plurality of data lines, a plurality of gate lines, and a plurality of pixel regions disposed in a matrix. The pixel region is configured by a plurality of sub pixels and includes transmission areas, circuit areas, and a plurality of emission areas which overlap with a part of the transmission areas and the circuit areas.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: August 25, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: EuiTae Kim, MinKi Kim, KiSeob Shin
  • Patent number: 10748944
    Abstract: A method for manufacturing an array substrate, including: forming a semiconductor material film on a substrate, the method further including: forming a metal film covering the semiconductor material film; and performing a single patterning process on the metal film and the semiconductor material film to form an active layer, a semiconductor material remained pattern and a first electrode of a storage capacitor. The semiconductor material remained pattern is in a same layer as the active layer; and the first electrode of the storage capacitor is formed of the metal film and is on a side, away from the substrate, of the semiconductor material remained pattern. An array substrate and a display device are also provided.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 18, 2020
    Assignees: HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kui Gong, Xianxue Duan, Cheng Chen
  • Patent number: 10746011
    Abstract: Apparatus, systems, and methods for ranging operate to use a wireline active ranging system to initially determine a relative distance and relative direction from a first well (e.g., ranging well) to a second well (e.g., target well) and an EM azimuthal logging tool to maintain or adjust the distance from the target well while drilling the ranging well. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: August 18, 2020
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Hsu-Hsiang Wu, Burkay Donderici
  • Patent number: 10741632
    Abstract: A display device including a first signal line disposed on a substrate, a first insulating layer disposed on the first signal line, and a second signal line disposed on the first insulating layer and crossing the first signal line, in which the first insulating layer includes a recess portion providing a surface height lower than other areas of the first insulating layer, and the first signal line and the second signal line overlap each other with the recess portion therebetween.
    Type: Grant
    Filed: December 31, 2018
    Date of Patent: August 11, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Pil Suk Lee, Jin Taek Kim, Ki Wan Ahn
  • Patent number: 10734493
    Abstract: A semiconductor memory device may include a substrate, gate electrode structures stacked on the substrate, insulation patterns between the gate electrode structures, vertical channels penetrating through the gate electrode structures and the insulation patterns, and a data storage pattern. The vertical channels may be electrically connected to the substrate. The data storage pattern may be arranged between the gate electrode structures and the vertical channels. Each of the gate electrode structures may include a barrier film, a metal gate, and a crystal grain boundary plugging layer. The crystal grain boundary plugging layer may be between the barrier film and the metal gate.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: August 4, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hauk Han, Je-hyeon Park, Do-hyung Kim, Tae-yong Kim, Keun Lee, Jeong-gil Lee, Hyun-seok Lim
  • Patent number: 10734461
    Abstract: An exemplary embodiment of the present invention provides a thin film transistor array panel and an organic light emitting diode display including the same including a substrate, a semiconductor disposed on the substrate, a first gate insulation layer disposed on the semiconductor, and a first diffusion barrier layer disposed on the first gate insulation layer. A second diffusion barrier layer is disposed on a lateral surface of the first diffusion barrier layer. A first gate electrode is disposed on the first diffusion barrier layer. A source electrode and a drain electrode are connected to the semiconductor. The first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: August 4, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Hee Lee, Hyun Ju Kang, Sang Won Shin
  • Patent number: 10727225
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a gate electrode, a fifth semiconductor region, a sixth semiconductor region, a seventh semiconductor region, an eighth semiconductor region, and a second electrode. The first semiconductor region is provided on the first electrode. The eighth semiconductor region surrounds the third semiconductor region, the sixth semiconductor region, and the seventh semiconductor region. The eighth semiconductor region includes a first region and a second region respectively arranged with the third semiconductor region and the seventh semiconductor region in a third direction. A lower end of the second region is positioned higher than a lower end of the first region.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 28, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Ryohei Gejo
  • Patent number: 10727292
    Abstract: Discussed is an electroluminescence display apparatus for preventing the performance, efficiency, and lifetime of a device from being reduced. The electroluminescence display apparatus includes a substrate including an active area including a plurality of pixels, a circuit element layer disposed on the substrate, a first electrode disposed on the circuit element layer, an auxiliary electrode disposed on the circuit element layer and spaced apart from the first electrode, a first light emitting layer disposed on the first electrode, a buffer layer disposed on the first light emitting layer, a second light emitting layer disposed on the buffer layer and the auxiliary electrode, and a second electrode disposed on the second light emitting layer.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 28, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Sungmoo Kim, Jinah Kwak, Sejin Kim
  • Patent number: 10720382
    Abstract: Disclosed are semiconductor package structure and semiconductor modules including the same. The semiconductor module includes a circuit board, a first semiconductor package over the circuit board, and a connection structure on the circuit board and connecting the circuit board and the first semiconductor package. The first semiconductor package includes a first package substrate. A difference in coefficient of thermal expansion between the connection structure and the circuit board may be less than a difference in coefficient of thermal expansion between the circuit board and the first package substrate.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: July 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: YoungJoon Lee, Sunwon Kang
  • Patent number: 10699961
    Abstract: Structures for switches and methods for forming structures that include a switch. A first well and a section well are arranged in a substrate. Trench isolation regions are arranged in the substrate to define multiple active device regions. Each of the active device regions includes a section of the first well that is surrounded by the trench isolation regions. The second well has an opposite conductivity type from the first well. The active device regions and the trench isolation regions are arranged between the top surface of the substrate and the second well, and the second well is contiguous with the trench isolation regions.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Edward J. Nowak
  • Patent number: 10700083
    Abstract: An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 30, 2020
    Assignee: LONGITUDE FLASH MEMORY SOLUTIONS LTD.
    Inventors: Krishnaswamy Ramkumar, Bo Jin, Fredrick B. Jenne
  • Patent number: 10700132
    Abstract: The present disclosure relates to a solid-state imaging device that can achieve a high S/N ratio at a high sensitivity level without any decrease in resolution, and to an electronic apparatus. In the upper layer, the respective pixels of a photoelectric conversion unit that absorbs light of a first wavelength are tilted at approximately 45 degrees with respect to a square pixel array, and are two-dimensionally arranged in horizontal directions and vertical directions in an oblique array. The respective pixels of a photoelectric conversion unit that is sensitive to light of a second or third wavelength are arranged under the first photoelectric conversion unit. That is, pixels that are ?2 times as large in size (twice as large in area) and are rotated 45 degrees are arranged in an oblique array. The present disclosure can be applied to solid-state imaging devices that are used in imaging apparatuses, for example.
    Type: Grant
    Filed: November 13, 2015
    Date of Patent: June 30, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Atsushi Toda
  • Patent number: 10679842
    Abstract: The present invention provides: an InP wafer optimized from the viewpoint of small edge roll-off (ERO) and sufficiently high flatness even in the vicinity of a wafer edge; and a method for effectively producing the InP wafer. The InP wafer having a roll-off value (ROA) of from ?1.0 ?m to 1.0 ?m is obtained by using a method including: performing a first stage polishing under a processing pressure of from 10 to 200 g/cm2 for a processing time of from 0.1 to 5 minutes, while supplying a polishing solution containing bromine to at least one side of an InP single crystal substrate that will form the InP wafer; and performing a second stage polishing under a processing pressure of from 200 to 500 g/cm2 for a processing time of from 0.5 to 10 minutes, provided that the processing pressure is higher than that of the first stage polishing by 50 g/cm2 or higher.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: June 9, 2020
    Assignee: JX Nippon Mining & Metals Corporation
    Inventors: Taku Yoshida, Hideki Kurita
  • Patent number: 10644019
    Abstract: A semiconductor device includes a peripheral circuit region on a substrate, a polysilicon layer on the peripheral circuit region, a memory cell array region on the polysilicon layer and overlapping the peripheral circuit region, the peripheral circuit region being under the memory cell array region, an upper interconnection layer on the memory cell array region, and a vertical contact through the memory cell array region and the polysilicon layer, the vertical contact connecting the upper interconnection layer to the peripheral circuit region.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yoo-cheol Shin, Young-woo Park, Jae-duk Lee
  • Patent number: 10642300
    Abstract: Systems and techniques enable monitoring one or more devices connected to an electrical power distribution system. In some implementations, a probe waveform is injected into a circuit of an electrical power distribution system. An output signal of the injected probe waveform is extracted from the circuit of the electrical power distribution system and, based on the extracted output signal of the injected probe waveform, dispersion values for the branch circuit are determined. The dispersion values indicate a variation of magnitude of an impedance of the branch circuit across different values of phase of the impedance. Based on the dispersion values for the branch circuit, at least one characteristic of a device connected to the branch circuit is determined. An association between the at least one characteristic of the device connected to the branch circuit and the corresponding dispersion values is stored in at least one computer memory.
    Type: Grant
    Filed: August 12, 2019
    Date of Patent: May 5, 2020
    Assignee: Alarm.com Incorporated
    Inventors: Alain Charles Briançon, Robert Leon Lutes