Abstract: The present disclosure relates to a semiconductor device and a method of fabricating the same, the semiconductor device including a substrate, an active structure and a shallow trench isolation. The active structure is disposed within the substrate, including a plurality of first active fragments and a plurality of second active fragments. The first active fragments and the second active fragments are parallel and separately extended along a first direction, and the second active fragments are disposed outside all of the first active fragments. The first active fragments have a same length in the first direction, being a first length, the second active fragment have a second length in the first direction, and the second length is greater than the first length.

Abstract: The present disclosure relates to a semiconductor device and its manufacturing method, and the semiconductor device includes a substrate, a channel layer, a gate electrode, a first electrode, a second electrode, and a metal plate. The channel layer is disposed on the substrate, and the gate electrode is disposed on the channel layer. The first electrode and the second electrode are disposed on the channel layer, at two opposite sides of the gate electrode respectively. The metal plate is disposed over the channel layer, between the first electrode and the gate electrode. The metal plate includes a first extending portion and a second extending portion, wherein the second extending portion extends towards the substrate without contacting the channel layer, and the first extending portion extends toward and directly contacts the first electrode or the second electrode.

Abstract: A semiconductor structure can include a high voltage region, a first moat trench isolation structure electrically insulating the high voltage region from low voltage regions of the semiconductor structure, and a second moat trench isolation structure electrically insulating the high voltage region from the low voltage regions of the semiconductor structure. The first moat trench isolation structure can include dielectric sidewall spacers and a conductive fill material portion located between the dielectric sidewall spacers. The second moat trench isolation structure can include only at least one dielectric material, and can include a dielectric moat trench fill structure having a same material composition as the dielectric sidewall spacers and having a lateral thickness that is greater than a lateral thickness of the dielectric sidewall spacers and is less than twice the lateral thickness of the dielectric sidewall spacers.

Abstract: A method of configuring a mark having a trench to be etched into a substrate, the method including: obtaining a relation between an extent of height variation across a surface of a probationary layer deposited on a probationary trench of a probationary depth and a thickness of the probationary layer; determining an extent of height variation across the surface of a layer deposited on the mark allowing a metrology system to determine a position of the mark; and configuring the mark by determining a depth of the trench based on the relation, the extent of height variation and the thickness of a process layer to be deposited on the mark.

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes an interconnect structure disposed over a substrate. The interconnect structure includes a plurality of interconnect layers disposed within a dielectric structure. A bond pad structure is disposed over the interconnect structure. The bond pad structure includes a contact layer. A first masking layer including a metal-oxide is disposed over the bond pad structure. The first masking layer has interior sidewalls arranged directly over the bond pad structure to define an opening. A conductive bump is arranged within the opening and on the contact layer.

Abstract: According to the present embodiment, a semiconductor device includes a semiconductor substrate, a memory transistor, and a MOS transistor. The memory transistor includes at least a first silicon dioxide film and a first gate electrode positioned on the semiconductor substrate in order. The MOS transistor includes a second silicon dioxide film and a second gate electrode positioned on the semiconductor substrate in order. Any bird's beak is not generated in at least either the first silicon dioxide film or the first gate electrode of the memory transistor.

Abstract: A laser processing apparatus includes a support part, a light source, a spatial light modulator, a converging part, and a controller. The controller controls the spatial light modulator so that laser light is branched into a plurality of rays of processing light including 0th-order light and a plurality of converging points for the plurality of rays of processing light are located at positions different from each other in a Z direction and an X direction, and controls at least one of the support part and the converging part. The controller controls the spatial light modulator so that a converging point of the 0th-order light in the Z direction is located on an opposite side of a converging point of non-modulated light of the laser light with respect to an ideal converging point of the 0th-order light.

Abstract: The present disclosure provides a manufacturing method of a semiconductor device, including: providing a substrate; forming a film stack structure on the substrate, a top of the film stack structure being a cover layer; forming a mask structure on the cover layer, the mask structure including a mask layer and a pattern transfer layer sequentially stacked from top to bottom; performing a first etching on the mask structure to form first blind holes, the first blind holes running through the mask structure and terminating in the cover layer; and performing a second etching on the mask structure, and removing the mask layer, to flatten a top surface of the pattern transfer layer and trim bottoms of the first blind holes.

Abstract: The disclosure provides a pixel array and a display device. The pixel array includes a plurality of sub-pixels, each of which has a virtual pixel center, the plurality of sub-pixels include first sub-pixels, second sub-pixels, and third sub-pixels; virtual centers of two first sub-pixels and two third sub-pixels are sequentially connected to form a second virtual quadrangle; a first virtual polygon includes four second virtual quadrangles in an array and sharing adjacent sides; and the first sub-pixels and the third sub-pixels are at vertex angles or sides of the first virtual polygon and are alternately on the vertex angles or the sides of the first virtual polygon along a clockwise direction; the first virtual polygon has a first virtual point therein, lines connecting the first virtual point and virtual centers of the four third sub-pixels on the first virtual polygon divide the first virtual polygon into four virtual isosceles trapezoids.

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate, the surface of the semiconductor substrate having a plurality of active areas and shallow trench isolation areas arranged in a first direction; etching the active areas and the shallow trench isolation areas in a direction perpendicular to the first direction to form first recesses and second recesses; covering the surfaces of the first recesses and the second recesses with an adhesive layer and a metal layer; and secondarily etching the metal layer and the adhesive layer in the direction perpendicular to the first direction to form a contact hole, the depth of the adhesive layer in the contact hole being defined as H2.

Abstract: A vertical gallium nitride (GaN) PN diode uses epitaxial growth of a thick drift region with a very low carrier concentration and a carefully designed multi-zone junction termination extension to achieve high voltage blocking and high-power efficiency. An exemplary large area (1 mm2) diode had a forward pulsed current of 3.5 A, an 8.3 m?-cm2 specific on-resistance, and a 5.3 kV reverse breakdown. A smaller area diode (0.063 mm2) was capable of 6.4 kV breakdown with a specific on-resistance of 10.2 m?-cm2, when accounting for current spreading through the drift region at a 45° angle.

Abstract: An array substrate comprises a substrate body, a plurality of first wires, a plurality of second wires and a plurality of connecting electrodes. The plurality of first wires are provided on a first conductive layer; the plurality of second wires are provided on a second conductive layer, and the first conductive layer and the second conductive layer are located in different layers; the plurality of connecting electrodes are provided on a third conductive layer, and the connecting electrodes are respectively connected to the first wires and the second wires so as to connect the corresponding first wires and second wires, wherein orthographic projection areas of the connecting electrodes on the base substrate are not exactly the same. The array substrate may solve a problem of inconsistent signal delays on the second wires due to inconsistent lengths of the second wires.

Abstract: A display substrate, an ink jet printing method and a display apparatus are provided. The display substrate includes a base substrate and a pixel define layer disposed on the base substrate, wherein the pixel define layer includes first define layers and a second define layer, a printing region is formed on the base substrate between the first define layers, and the second define layer is disposed on the printing region and divides the printing region into at least two sub-printing regions, and a height of the first define layers is greater than that of the second define layer in a direction perpendicular to the base substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of channel layers stacked over a semiconductor substrate and spaced apart from one another, a source/drain structure adjoining the plurality of channel layers, a gate structure wrapping around the plurality of channel layers, and a first inner spacer between the gate structure and the source/drain structure and between the plurality of channel layers. The first inner spacer is made of an oxide of a semiconductor material.

Abstract: A display panel and display apparatus. The display panel includes a first display area, a second display area, and an isolation area. A light transmittance of the first display area is greater than a light transmittance of the second display area. At least a part of the isolation area is positioned between the first display area and the second display area. The display panel includes a plurality of first sub-pixels positioned in the first display area; a first pixel circuit positioned in the second display area, the first pixel circuit being electrically connected to the first sub-pixels in the first display area and being configured to drive the first sub-pixels in the first display area to display; and a light-blocking assembly positioned in the isolation area, the light-blocking assembly being configured to block light incident from the first sub-pixels to the first pixel circuit.

Abstract: Contact over active gate (COAG) structures with a tapered gate or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers. A conductive structure is in direct contact with the conductive cap and sidewall spacers on one of the plurality of gate structures or with the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures.

Abstract: The organic electroluminescence display device of an embodiment of the present invention includes a substrate, a plurality of pixels formed on the substrate, and a sealing film that covers the plurality of pixels. The sealing film includes a first barrier layer, a base layer covering the top surface of the first barrier layer, an inter layer locally formed on the top surface of the base layer, and a second barrier layer covering the top surface of the base layer and the top surface of the inter layer. The inter layer is formed so as to cover a step on the top surface of the base layer.

Abstract: A semiconductor device includes: a semiconductor substrate; a transistor formed on the semiconductor substrate; a first insulating layer adjacent to the transistor in a first direction along a main surface of the semiconductor substrate, the first insulating layer being formed toward an inside of the semiconductor substrate; a first conductive layer connected to a gate of the transistor, a part of the first conductive layer being opposed to the first insulating layer; a second insulating layer disposed between the first insulating layer and the first conductive layer; and a first semiconductor layer disposed between the second insulating layer and the first conductive layer.

Abstract: A semiconductor device includes a base, a detector on the base and including a first surface on which a detection portion is provided, and a resin package on the base and including an exposure hole to externally expose the detection portion of the detector. At least a portion of an outer peripheral edge of the first surface of the detector is exposed in the exposure hole. The resin package includes a depressed portion along the portion of the outer peripheral edge that is exposed in the exposure hole.

Abstract: A display device includes a substrate including an emission area and a non-emission area and in which a plurality of sub-pixels are defined, first electrodes disposed in the plurality of sub-pixels, respectively, a bank that is disposed in the non-emission area between the plurality of sub-pixels, and exposes the first electrode through an opening, a protrusion disposed in a second non-emission area of the non-emission area which is divided into a first non-emission area at a flat top surface of the bank and the second non-emission area at an inclined top surface of the bank, an organic layer disposed on the first electrodes, and a second electrode disposed on the organic layer.