Patents Examined by Peter Bradford
  • Patent number: 10319947
    Abstract: According to one embodiment, an organic semiconductor device includes a supporting substrate, a plurality of organic EL light emitting elements, a first barrier layer, a flattening layer, and a second barrier layer. The flattening layer exists sporadically and makes gentle in inclination steep elevation change present in the surface of the first barrier layer. The first barrier layer and the second barrier layer are made of moisture penetration preventive material.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 11, 2019
    Assignee: Japan Display Inc.
    Inventors: Daisuke Kato, Kaichi Fukuda
  • Patent number: 10319809
    Abstract: A semiconductor device contains an LDNMOS transistor with a lateral n-type drain drift region and a p-type RESURF region over the drain drift region. The RESURF region extends to a top surface of a substrate of the semiconductor device. The semiconductor device includes a shunt which is electrically coupled between the RESURF region and a low voltage node of the LDNMOS transistor. The shunt may be a p-type implanted layer in the substrate between the RESURF layer and a body of the LDNMOS transistor, and may be implanted concurrently with the RESURF layer. The shunt may be through an opening in the drain drift region from the RESURF layer to the substrate under the drain drift region. The shunt may be include metal interconnect elements including contacts and metal interconnect lines.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: June 11, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Yongxi Zhang, Philip L. Hower, John Lin, Guru Mathur, Scott G. Balster, Constantin Bulucea, Zachary K. Lee, Sameer P. Pendharkar
  • Patent number: 10319746
    Abstract: A display device is disclosed, which comprises: a substrate; a first metal conductive layer disposed on the substrate; a semiconductor layer disposed on the first metal conductive layer and having a top surface; and a second metal conductive layer disposed on the top surface and comprising a first part and a second part. Herein, a first extending direction is defined as a direction that the first part extends toward the second part, the first part has a maximum length in a first region that the first part overlaps the first metal conductive layer along the first extending direction, the first part has a maximum width in a second region that the first part overlaps the semiconductor layer along a second direction vertical to the first extending direction, and the maximum length is greater than the maximum width and less than or equal to twice of the maximum width.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 11, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: An-Chang Wang, Bo-Chin Tsuei, Hsia-Ching Chu, Ming-Chien Sun
  • Patent number: 10312461
    Abstract: The present disclosure provides a flexible organic light-emitting diode (OLED) display panel including a flexible substrate and a plurality of thin film transistor (TFT) devices disposed on the flexible substrate. The flexible substrate comprises: a first polyimide (PI) layer; a first inorganic barrier layer disposed on a surface of the first PI layer; a titanium metal layer disposed on a surface of the first inorganic barrier layer; a second PI layer disposed on a surface of the titanium metal layer; and a second inorganic barrier layer disposed on a surface of the second PI layer. The TFT devices are disposed on a surface of the second inorganic barrier layer.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: June 4, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Fang Qin
  • Patent number: 10303919
    Abstract: An optical sensor for imaging an input object, such as a fingerprint, on a sensing region of a display is disclosed. The sensor includes a transparent substrate having a first side and a second side opposite the first side. An array of detector elements is positioned above the first side of the transparent substrate and an angle limiting reflector is positioned below the second side of the transparent substrate. The angle limiting reflector is configured to reflect light incident on the angle limiting reflector within a limited acceptance angle towards the array detector elements.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: May 28, 2019
    Assignee: Synaptics Incorporated
    Inventors: Marek Mienko, Patrick Smith, Arash Akhavan Fomani, Jeffrey A. Small
  • Patent number: 10304923
    Abstract: A method of manufacturing a semiconductor die includes forming a semiconductor body on a substrate. The semiconductor body has a periphery which is devoid of active devices and terminates at an edge face of the semiconductor die. The semiconductor body includes a first III-nitride semiconductor layer and a plurality of second III-nitride semiconductor layers below the first III-nitride semiconductor layer. The method further includes forming an uninsulated connection structure which extends vertically in the periphery of the semiconductor body and provides a vertical leakage path for at least some of the second III-nitride semiconductor layers either to the substrate or to a metallization layer disposed above the semiconductor body, but not to both. Additional semiconductor die manufacturing methods are provided.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Clemens Ostermaier, Gerhard Prechtl, Oliver Häberlen
  • Patent number: 10297724
    Abstract: A light-emitting device mounting package includes a substrate, a frame extending upward from the substrate and surrounding a mounting portion, a lead plate supported on the frame, and a ceramic plate having a facing front surface and a facing back surface on the opposite side. The frame has a first through hole through which the lead terminal extends. The ceramic plate has a second through hole, and a metalized layer formed on the facing front surface such that the metalized layer is spaced from an opening of the second through hole. The lead plate penetrates the first and second through holes and is fixed, via a collar portion, to a region of the facing back surface around an opening of the second through hole on the facing back surface side. The insulating member is fixed to a region around the first through hole via the metalized layer.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 21, 2019
    Assignee: NGK SPARK PLUG CO., LTD.
    Inventors: Masahito Morita, Kenji Suzuki
  • Patent number: 10297793
    Abstract: An organic electroluminescent device is provided. The organic electroluminescent device includes a transparent electrode layer; a reflective electrode layer; and an organic functional layer between the transparent electrode layer and the reflective electrode layer. The organic functional layer includes an emitting-material layer for emitting light; and further includes a first medium functional layer between the emitting-material layer and the reflective electrode layer and a second medium functional layer between the first medium functional layer and the reflective electrode layer. The first medium functional layer is optically denser than the second medium functional layer; and the first medium functional layer and the second medium functional layer are configured to cause at least a part of the light emitted undergoing a total reflection at the interface between the first medium functional layer and the second medium functional layer.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: May 21, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Jiandong Bao, Minhui Jia
  • Patent number: 10297667
    Abstract: A method of forming a semiconductor structure includes forming a nanosheet stack disposed over a first portion of a substrate and a fin channel material disposed over a second portion of the substrate, patterning the nanosheet stack disposed over the first portion of the substrate to form two or more nanosheet channels for at least one nanosheet field-effect transistor, patterning the fin channel material disposed over the second portion of the substrate to form one or more fins for at least one fin field-effect transistor, forming a first dielectric layer surrounding the nanosheet channels and the one or more fins, patterning a mask layer over the one or more fins, removing the first dielectric layer surrounding the nanosheet channels, removing the mask layer, forming a second dielectric layer surrounding the nanosheet channels and over the first dielectric layer surrounding the one or more fins, and forming a gate conductive layer over the second dielectric layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 21, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chun Wing Yeung, Chen Zhang, Peng Xu, Huiming Bu, Kangguo Cheng
  • Patent number: 10284300
    Abstract: Disclosed are structures and methods for a monolithic silicon (Si) coherent transceiver with integrated laser and gain elements wherein an InP chip is bonded to the Si chip in a recess formed in that Si chip.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: May 7, 2019
    Assignee: Acacia Communications, Inc.
    Inventors: Christopher Doerr, Long Chen
  • Patent number: 10273794
    Abstract: Apparatus, systems, and methods for ranging operate to use a wireline active ranging system to initially determine a relative distance and relative direction from a first well (e.g., ranging well) to a second well (e.g., target well) and an EM azimuthal logging tool to maintain or adjust the distance from the target well while drilling the ranging well. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 30, 2019
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Hsu-Hsiang Wu, Burkay Donderici
  • Patent number: 10270059
    Abstract: A flexible display and manufacturing method thereof are disclosed. In one aspect, the flexible display includes a flexible substrate including a bending area, an insulating layer disposed on the flexible substrate, and at least one groove in the insulating layer within the bending area. The flexible display also includes a stress relaxation layer disposed on the at least one groove and a plurality of wires formed over the insulating layer and the stress relaxation layer.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: April 23, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Nam Jin Kim
  • Patent number: 10263212
    Abstract: Provided is an organic light emitting display device in which a plurality of pixel areas each including an emitting area and a non-emitting area is defined in a display area. The organic light emitting display device includes: an auxiliary electrode in a part of a non-emitting area of at least one pixel area; an auxiliary electrode contact portion formed as a part of the auxiliary electrode; a first electrode in the emitting areas of the plurality of pixel areas; an organic layer on the first electrode and the auxiliary electrode; and a second electrode on the organic layer. The auxiliary electrode contact portion electrically connects the auxiliary electrode and the second electrode. A distance from a center of the auxiliary electrode contact portion to a terminal end of the first electrode in the emitting area may be 3 ?m or more.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: April 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Junho Lee
  • Patent number: 10262222
    Abstract: The invention relates to a method for measuring dimensions of a target object. The method comprises acquiring depth data representative of the physical space, the depth data comprising data of the target object, converting the depth data into a point cloud, extracting at least one plane from the point cloud, identifying a ground plane, eliminating the ground plane from the point cloud, extracting at least one point cluster from the remaining point cloud, identifying a point cluster of the target object, estimating dimensions of the target object based on the point cluster of the target object.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: April 16, 2019
    Assignee: SICK INC.
    Inventors: Alexander Shteinfeld, Richard Lydon, George Liu, Udrekh Gavale
  • Patent number: 10249725
    Abstract: A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, a first insulating layer, a gate metal layer, a via, a first source metal layer, a drain metal layer, and a second source metal layer. The source electrode, the drain electrode, and the gate electrode are present on the active layer. The first insulating layer is present on the source electrode, the drain electrode, and the gate electrode. The gate metal layer, the first source metal layer, the second source metal layer, and the drain metal layer are present on the first insulating layer. The gate metal layer includes a narrow portion and a wider portion. The via is present between the metal gate layer and the gate electrode. The second source metal layer is present between the gate metal layer and the drain metal layer.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: April 2, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Li-Fan Lin, Chun-Chieh Yang
  • Patent number: 10230049
    Abstract: Provided herein are perovskite-polymer films, methods of forming polymer-perovskite films, and devices including polymer-perovskite films. The polymer-perovskite films may include a plurality of methylammonium lead chloride (CH3NH3PbCl3) nanopillar crystals embedded in a polymer matrix. The devices can be optoelectronic devices, such as light emitting diodes, which include polymer-perovskite films. The polymer-perovskite films of the devices can be hole transport layers in the devices. The methods of making films may include spin casting a precursor solution followed by thermal annealing.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: March 12, 2019
    Assignee: Florida State University Research Foundation, Inc.
    Inventors: Biwu Ma, Hanwei Gao, Yu Tian, Yichuan Ling
  • Patent number: 10194522
    Abstract: A method comprises applying an adhesive to a first substrate and a second substrate to secure the first substrate to the second substrate. The adhesive extends in a plane on one side of an interposer that also extends in the plane, and is contiguous with the adhesive. The interposer comprises openings to enable flow of adhesive through the openings to form adhesive bond areas on one of the substrates where the areas substantially conform to the openings and lie adjacent to adhesive free areas. The adhesive substantially covers the other of the substrates so that the bond areas produce regions of reduced adhesive strength to the one substrate compared to the bond strength of the adhesive to the other substrate. Adjusting opening sizes adjusts area bond strengths. One substrate may comprise a VTM, the other a heat spreader, and the adhesive, a TIM. An article of manufacture comprises the substrate-adhesive-interposer-adhesive-substrate layers.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: January 29, 2019
    Assignee: International Business Machines Corporation
    Inventors: Timothy J. Chainer, Michael Gaynes
  • Patent number: 10192944
    Abstract: An exemplary embodiment of the present invention provides a thin film transistor array panel and an organic light emitting diode display including the same including a substrate, a semiconductor disposed on the substrate, a first gate insulation layer disposed on the semiconductor, and a first diffusion barrier layer disposed on the first gate insulation layer. A second diffusion barrier layer is disposed on a lateral surface of the first diffusion barrier layer. A first gate electrode is disposed on the first diffusion barrier layer. A source electrode and a drain electrode are connected to the semiconductor. The first diffusion barrier layer comprises a metal, and the second diffusion barrier layer comprises a metal oxide including the metal.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Dong Hee Lee, Hyun Ju Kang, Sang Won Shin
  • Patent number: 10170711
    Abstract: A thin-film transistor layer, an organic light-emitting diode layer, and other layers may be used in forming an array of pixels on a substrate in a display. Vias may be formed through one or more layers of the display such as the substrate layer to form vertical signal paths. The vertical signal paths may convey signals between display driver circuitry underneath the display and the pixels. The vias may pass through a polymer layer and may contact pads formed within openings in the substrate. Vias may pass through a glass support layer. Metal traces may be formed in the thin-film transistor layer to create signal paths such as data lines and gate lines. Portions of the metal traces may form vias through a polymer layer such as a substrate layer or a polymer layer that has been formed on top of the substrate layer.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: January 1, 2019
    Assignee: Apple Inc.
    Inventors: Jason C. Sauers, Jean-Pierre S. Guillou, Peter J. Kardassakis, Shaowei Qin, Yi Tao
  • Patent number: 10163649
    Abstract: A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, at least one conductive plug, and at least one protection layer. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure. The protection layer is present between the conductive plug and the spacer.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng