Abstract: A semiconductor light emitting device includes a first semiconductor layer, an active layer disposed on the first semiconductor layer to emit ultraviolet light, a second semiconductor layer disposed on the active layer, and a first electrode disposed on the first semiconductor layer and being in Ohmic contact with a portion of the first semiconductor layer, the first electrode including a contact electrode including aluminum (Al) and at least one other material and having a first region adjacent to the first semiconductor layer and a second region, with each region having an Al composition ratio defined by the amount of Al relative to the amount of the at least one other material. The Al composition ratio of the first region is greater than the Al composition ratio of the second region, and a metal layer disposed on the contact electrode.

Abstract: The present disclosure provides a lighting device and a manufacturing method thereof. The lighting device of an embodiment includes a substrate, a light emitting unit and a light adjusting layer. The light emitting unit is disposed on the substrate, and the light emitting unit includes a light output surface. The light adjusting layer is disposed on the light emitting unit, and the light adjusting layer includes a first portion and a second portion connected to the first portion. Wherein, the first portion only partially covers the light output surface, and the second portion does not cover the light output surface.

Abstract: A molded semiconductor package includes a lead frame having one or more first leads monolithically formed with a die pad and extending outward from the pad in a first direction. A semiconductor die is attached to the die pad at a first side of the die. A metal clip of a clip frame is attached to a power terminal at a second side of the die. One or more second leads monolithically formed with the metal clip extend outward from the clip in a second direction different than the first direction. A mold compound embeds the die. The first lead(s) and the second lead(s) are exposed at different sides of the mold compound and do not vertically overlap with one another. Within the mold compound, the clip transitions from a first level above the power terminal to a second level in a same plane as the leads.

Abstract: An example integrated circuit die includes: lower level conductor layers, lower level insulator layers between the lower level conductor layers, lower level vias extending vertically through the lower level insulator layers, upper level conductor layers overlying the lower level conductor layers, upper level insulator layers between and surrounding the upper level conductor layers, upper level vias; at least two scribe seals arranged to form a vertical barrier extending vertically from the semiconductor substrate to a passivation layer at an upper surface of the integrated circuit die; and at least one opening extending vertically through one of the at least two scribe seals and extending through: the upper level conductor layers, the upper level via layers, the lower level conductor layers, and the lower level via layers.

Abstract: A display panel and a manufacturing method are provided, wherein the display panel includes an array substrate, a first anode layer, a pixel definition layer, a second anode layer, a light-emitting layer, and a cathode layer. The array substrate includes an array area. The first anode layer is disposed on the array area. The pixel definition layer disposed on the array area and the first anode layer includes a plurality of holes and a first area. The second anode layer is disposed on the first area. The light-emitting layer is disposed in the plurality of holes. The cathode layer is disposed on the pixel definition layer and the light-emitting layer.

Abstract: A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

Abstract: According to one embodiment, a semiconductor device includes a substrate, an interconnect layer, a layer stack, and a first silicon nitride layer. The interconnect layer includes a transistor provided on the substrate and a first interconnect electrically coupled to the transistor and is provided above the transistor. The layer stack is provided above the interconnect layer and includes conductive layers stacked with an insulation layer interposed between two of conductive layers of each pair of conductive layers. The first silicon nitride layer is provided between the interconnect layer and the layer stack.

Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion.

Abstract: Disclosed is a display module that includes a substrate including a plurality of interconnection wires, a connecting member comprising a conductive material disposed on one side of the substrate, a plurality of inorganic light emitting elements comprising light emitting circuitry arranged on the connecting member, and a light blocking member comprising an opaque material disposed on a region other than regions where the plurality of inorganic light emitting elements are disposed. A portion of each of the plurality of inorganic light emitting elements is disposed to pass through a portion of the connecting member and is spaced apart from the substrate. The connecting member electrically connects each of the plurality of inorganic light emitting elements with at least one interconnection wire among the plurality of interconnection wires. The light blocking member is spaced apart from the substrate and disposed on the connecting member.

Abstract: A method for making a heteroepitaxial layer. The method comprises providing a semiconductor substrate. A seed area delineated with a selective growth mask is formed on the semiconductor substrate. The seed area comprises a first material and has a linear surface dimension of less than 100 nm. A heteroepitaxial layer is grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material. Devices made by the method are also disclosed.

Abstract: Provided is an organic light emitting display device, which includes a substrate including a display area including a plurality of sub-pixels and a non-display area other than the display area; an overcoat layer on the substrate; a plurality of first electrodes disposed on the overcoat layer in the plurality of sub-pixels; a first bank disposed in the display area and the non-display area and including a plurality of first openings exposing the plurality of first electrodes; a second bank disposed on the first bank in the display area and the non-display area and including a plurality of second openings exposing the plurality of first electrodes arranged in one direction; and a plurality of organic light emitting layers disposed in the plurality of second openings, respectively, wherein at least one among the plurality of second openings is split into at least two branch lines in the non-display area.

Abstract: An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing is between the parallel signal traces for a majority portion of the parallel signal traces.

Abstract: In a method of fabricating a nonvolatile memory device according an embodiment, a first tunnel oxide layer, a nitrogen supply layer, and a second tunnel oxide layer having a density lower than that of the first tunnel oxide layer are formed on a substrate. Nitrogen in the nitrogen supply layer is diffused into the second tunnel oxide layer to convert at least a portion of the second tunnel oxide layer into an oxynitride layer.

Abstract: An integrated circuit (IC) die is disclosed. The IC die can include a signal via extending through the IC die. The IC die can include a transmission line extending laterally within the IC die in a direction non-parallel to the signal via, the transmission line configured to transfer an electrical signal to the signal via. The IC die can include a matching circuit disposed between the transmission line and the signal via. The matching circuit can include inductance and capacitance matching circuitry to compensate for parasitic inductance and capacitance introduced by transition from the IC die to an underlying carrier.

Abstract: A switching device is disclosed. The switching device includes a spin-orbit coupling (SOC) layer, a pure spin conductor (PSC) layer disposed atop the SOC layer, a ferromagnetic (FM) layer disposed atop the PSC layer, and a normal metal (NM) layer sandwiched between the PSC layer and the FM layer. The PSC layer is a ferromagnetic insulator (FMI) is configured to funnel spins from the SOC layer onto the NM layer and to further provide a charge insulation so as to substantially eliminate current shunting from the SOC layer while allowing spins to pass through. The NM layer is configured to funnel spins from the PSC layer into the FM layer.

Abstract: An integrated circuit (IC) die having a first side and a second side opposite the first side is disclosed. The IC die can include a signal via through the IC die. The IC die can include processing circuitry. The IC die can include transition circuitry providing electrical communication between the processing circuitry and the signal via. The transition circuitry can comprise a first transmission line, a second transmission line, and a transition transmission line between the first and second transmission lines. In various embodiments, the first transmission line can comprise a microstrip (MS) line, and the second transmission line can comprise a grounded coplanar waveguide (CPW).

Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

Abstract: Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.

Abstract: A method of forming a deep trench isolation in a radiation sensing substrate includes: forming a trench in the radiation sensing substrate; forming a corrosion resistive layer in the trench, in which the corrosion resistive layer includes titanium carbon nitride having a chemical formula of TiCxN(2-x), and x is in a range of 0.1 to 0.9; and filling a reflective material in the trench and over the corrosion resistive layer.

Abstract: An electroluminescent display device includes first, second, third and fourth pixels arranged in a matrix form along a first direction and a second direction, each of the first, second, third and fourth pixels including first, second and third sub-pixels; a light-emitting diode disposed at each of the first, second and third sub-pixels and including a first electrode, a light-emitting layer and a second electrode, wherein the second sub-pixel is disposed between the first sub-pixel and the third sub-pixel; and a first bank is disposed between adjacent sub-pixels of a same color, and a second bank is disposed between adjacent sub-pixels of different colors, wherein the second sub-pixels of the first, second, third and fourth pixels surround the first sub-pixels of the first, second, third and fourth pixels.