Abstract: An existing design of an integrated circuit includes existing cells that have already been placed and routed. An engineering change order (ECO) specifies additional new cells (ECO cells) to be inserted into the existing design. The ECO cells are also associated with target locations for their placement among the existing cells, but these target locations may violate design rules. The feasibility of “legalizing” the placement of the ECO cells within the existing design is assessed as follows. The ECO cells are clustered into clusters based on their target locations. Clusters are assessed by determining an ECO placement impact (EPI) index for individual clusters. The EPI index is a measure of the feasibility for legalizing the placement of the ECO cells in that cluster.

Abstract: A failure analysis apparatus is an apparatus for analyzing a failure of a semiconductor device including a memory circuit and includes a storage device and a processor. The storage device stores EDA data including size values of a memory cell in the memory circuit, size values of a peripheral circuit in the memory circuit and arrangement spacing values of the peripheral circuit, and layout data of the semiconductor device. The processor converts logical addresses and I/O value of a fail bit obtained by testing the memory circuit into physical addresses using predetermined arithmetic expressions, and converts the physical addresses into physical coordinate values using the size values of the memory cell, the size values of the peripheral circuit, and the arrangement spacing values of the peripheral circuit.

Abstract: Various implementations described herein are directed to a method. The method may provide a tile database with multiple tiles that define one or more first component sections for a memory device. The method may define an array of storage elements having a specified memory array width. The method may define one or more second component sections having at least part of a standard cell based tile with standard cells arranged in multiple standard cell rows. The method may generate a memory instance by defining a layout for the memory device with the multiple tiles selected from the tile database based on matching the multiple standard cell rows to the specified memory array width of the array of storage elements.

Abstract: An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.

Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Abstract: Aiming at a hardness mismatch phenomenon in the existing structure hardness design process according to an integral intensity viewpoint, the invention provides a quantitative matching design method for structure heat treatment-hardness distribution. The specific method comprises determining an ideal static intensity field distribution of the dangerous section of the structure according to a limit static stress distribution of a dangerous section of the structure; determining an ideal hardness distribution of the dangerous section of the structure by utilizing an intensity-hardness conversion relation; determining heat treatment requirements such as surface hardness, core hardness and the like by combining material and heat treatment mode; determining an actual hardness distribution of the dangerous section of the structure according to a material end quenching curve and the heat treatment requirement.

Abstract: Systems and methods for assembling and developing a System-on-a-chip (SoC) by using templates and designer input data are described. One of the methods includes receiving a request for generating a design of the SoC. In response to the request, a template database is accessed to provide templates of a plurality of designs of systems-on-chips (SoCs). Each of the templates is for a technology application. The method includes receiving a selection of one of the templates. The one of the templates represents components of the SoC. The method also includes receiving a configuration file including configuration data input for the components of the SoC. The method includes compiling the configuration file and a definition file for the SoC to generate design files for the SoC.

Abstract: A circuit architecture for expanded design for testability functionality is provided that includes an Intellectual Property (IP) core for use with a design for an integrated circuit (IC). The IP core provides an infrastructure harness circuit configured to control expanded design for testability functions available within the IC. An instance of the IP core can be included in a circuit block of the design for the IC. The infrastructure harness circuit can include an outward facing interface configured to connect to circuitry outside of the circuit block and an inward facing interface configured to connect to circuitry within the circuit block. The instance of the IP core can be parameterized to configure the infrastructure harness circuit to control a plurality of functions selected from the expanded design for testability functions based on a user parameterization of the instance of the IP core.

Abstract: A scan chain engine can determine a set number of EXTEST scan chains for the IP block and based on a predetermined maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine iteratively executes partitioning on the IP block to generate a set of partitions. Each partition in the set of partitions has a number of EXTEST wrapper cells that does not exceed the maximum number of EXTEST wrapper cells per EXTEST scan chain. The scan chain engine selectively merges partitions of the set of partitions to form a set of populated partitions that each include an EXTEST wrapper cell. The number of partitions is equal to the set number of EXTEST scan chains for the IP block. The scan chain engine generates wire paths connecting EXTEST wrapper cells of each populated partition to construct the set number of EXTEST scan chains for the IP block.

Abstract: Aggregation of coverage data for a design-under-test (DUT) can be performed using a coverage testbench without running any simulations on the DUT. Stimulus data that was used previously for performing different simulations on the DUT can be saved in a database. The coverage testbench can read the saved stimulus data and aggregate the coverage data from the stimulus data using a coverage model. When the DUT is updated, the coverage model can be updated, and updated coverage data can be collected using the coverage testbench without re-running the simulations on the DUT.

Abstract: A method for fabricating an integrated circuit is provided. The method includes: receiving a cell schematic of a unit cell of the integrated circuit; when an intrinsic gain of a transistor of the unit cell falls outside a predetermined range of gain values, revising a set of parameter values for a set of size parameters of the unit cell in the cell schematic, wherein the intrinsic gain of the transistor of the unit cell characterized by the revised set of parameter values falls within the predetermined range of gain values; generating a cell layout of the unit cell according to the cell schematic indicating the revised set of parameter values for the set of size parameters; and fabricating the integrated circuit according to the cell layout of the unit cell.

Abstract: Performing partition wire assignment for routing a multi-partition circuit design can include performing, using computer hardware, a global assignment phase by clustering a plurality of super-long lines (SLLs) into a plurality of SLL bins, clustering loads of nets of a circuit design into a plurality of load clusters, and assigning the plurality of SLL bins to the plurality of load clusters. For each SLL bin, a detailed assignment phase can be performed wherein each net having a load cluster assigned to the SLL bin is assigned one or more particular SLLs of the SLL bin using the computer hardware.

Abstract: A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.

Abstract: A multi-bit standard cell embodied on a non-transitory computer-readable medium includes: a first logic cell with a first logic cell height measured from a first lower boundary to a first upper boundary of the first logic cell; and a second logic cell with a second logic cell height measured from a second lower boundary to a second upper boundary of the second logic cell, the second logic cell height different from the first logic cell height, and the second upper boundary attached to the first lower boundary. The first logic cell is arranged to perform a first logical function, the second logic cell is arranged to perform a second logical function, and the first logical function is the same as the second logical function.

Abstract: Various aspects of the disclosed technology relate to predicting physical failure analysis-oriented diagnosis resolution. Fault simulation is performed on a circuit design to derive test responses for a set of faults and test patterns for testing circuits fabricated according to the circuit design. The set of faults is grouped into groups of equivalent faults based on the test responses. A group of equivalent faults consists of faults having the same test responses for all test patterns in the test patterns that can activate the faults. A PFA (physical failure analysis)-oriented diagnosis resolution evaluation value is computed by averaging weighted sizes of the groups of equivalent faults. The weight factors for the groups of equivalent faults with sizes greater than a certain number being smaller than the weight factors for rest of the groups of equivalent faults.

Abstract: Disclosed herein is a method of designing a programmable logic device (PLD), in accordance with some embodiments. Accordingly, the method comprises transmitting module indications corresponding to application modules to a client device. Further, the method comprises receiving Hardware Description Language (HDL) code expressing a design of a PLD from the client device. Further, the method comprises analyzing the HDL code. Further, the method comprises retrieving an application module and a framework module corresponding to an API call based on the analyzing. Further, the method comprises instantiating the framework module and the application module based on the retrieving. Further, the method comprises configuring common synchronous logic components and an interconnect infrastructure based on the API call. Further, the method comprises generating a flat framework circuit data corresponding to the PLD based on the instantiating and the configuring.

Abstract: Various embodiments described herein use a set of capacitor sets (e.g., capacitor banks) in a power backup architecture for a memory sub-system, where each capacitor set can be individually checked for a health condition (e.g., in parallel) to determine their respective health after the memory sub-system has completed a boot process. In response to determining that at least one capacitor set has failed the health condition (or a certain number of capacitor sets have failed the health condition), the memory sub-system can perform certain operations prior to primary power loss to the memory sub-system (e.g., preemptively performs a data backup process to ensure data integrity) and can adjust the operational mode of the memory sub-system (e.g., switch it from read-write mode to read-only mode).

Abstract: A system for charging an electrical energy store by means of a converter. The converter monitors an electrical connection between the converter and the electrical energy store. If an interruption of the electrical connection between the converter and the electrical energy store is detected, for example, the opening of a circuit breaker between the electrical energy store and the converter, the further provision of electrical power for charging the electrical energy store through is immediately prevented by the converter.

Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Abstract: A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.