Abstract: A battery charging assembly includes a load management system, a charging cord with a battery connector, and circuitry for detecting thermal buildup. The load management system monitors the heat buildup in a coiled portion of the charging cord and issues a corresponding signal to control the current flowing through the cord.

Abstract: A method for stabilizing bandgap voltage includes the steps of: providing a first layout pattern designated with a first voltage; reducing a critical dimension of the first layout pattern for generating a second layout pattern corresponding to a second voltage; matching the second voltage with a target voltage; and then outputting the second layout pattern to a mask. Preferably, the first layout pattern and the second layout pattern include polysilicon resistor patterns.

Abstract: Systems and methods are disclosed for generation and testing of integrated circuit designs with clock crossings between clock domains. These may allow for the rapid design and testing (e.g. silicon testing) of processors and SoCs. Clock crossings may be automatically generated between modules, inferring the values of design parameters, such as a signaling protocol (e.g. a bus protocol), directionality, and/or a clock crossing type (e.g., synchronous, rational divider, or asynchronous), of a clock crossing. For example, implicit classes may be used to generate clock crossings in a flexible manner. For example, these system and methods may be used to rapidly connect a custom processor design, including one or more IP cores, to a standard input/output shell for a SoC design to facilitate rapid silicon testing of the custom processor design.

Abstract: Embodiments of the present disclosure describe methods, apparatuses, storage media, and systems for in-field safety tests on system-level and circuit-level, providing real-time and on-chip tests with respect to, including but not limited to, circuit reliability, power consumption, and system safety. The in-field safety tests may include implementing voltage droop monitors (VDMs) and signature collectors with authentication-enabled launching. Other embodiments may be described and claimed.

Abstract: Verifying a product is disclosed. An image of a self-assembly (SA) pattern on a substrate from a scanner is received. The SA pattern has been initially created using a block copolymer (BCP) which has been annealed on the substrate. Data from the SA pattern is stored in a computer system. The SA pattern data is associated with the product. The SA pattern is an information carrying security mark having a set of features with corresponding locations within the information carrying security mark which uniquely identify the product.

Abstract: An example operation may include one or more of generating a noise map which comprises one or more noise shapes for one or more electrical components on a substrate of a circuit, modifying a design of the one or more electrical components in a pre-production design of the circuit based on the noise map and one or more noise rules of the circuit, and outputting an updated design of the circuit which includes the modified design of the one or more electrical components.

Abstract: A physical verification tool for debugging ESD ground path resistance violations in ESD protection circuits. The ESD ground path is modeled and partitioned into component path structures (polygons) that are disposed in associated design layers. A total ESD ground path resistance is then calculated and compared with a maximum allowable resistance value defined by an ESD protection rule. When the ESD ground path is non-compliant, a resistance contribution ratio is determined for each polygon and/or for each layer, for example, by applying nodal analysis to the ESD ground path model. Resistance contribution ratios are then calculated for each polygon and/or for each layer, and most-problematic polygons and/or layers are identified by way of having the highest resistance contribution ratio values. A report (e.g., a table or graphical visualization) is then generated that prioritizes or emphasizes (e.g., by way of a bolder contrast or brighter color) the most-problematic layer and/or polygon.

Abstract: Embodiments of the present invention are directed to a cell protection system that may be employed in high voltage systems such as grid scale energy storage systems. In some embodiments, the advanced cell protection system includes a proactive balancing system for balancing one or more battery units of the energy storage systems. In some embodiments, the advanced cell protection system includes a switching protection system for safely connecting and disconnecting the one or more battery units of the energy storage systems to other systems. In some embodiments, the advanced cell protection system includes an isolated communication system for allowing the one or more battery units to safely communicate with each other and at least one controller of the energy storage system.

Abstract: A substrate having a plurality of features for use in measuring a parameter of a device manufacturing process and associated methods and apparatus. The measurement is by illumination of the features with measurement radiation from an optical apparatus and detecting a signal arising from interaction between the measurement radiation and the features. The plurality of features include first features distributed in a periodic fashion at a first pitch, and second features distributed in a periodic fashion at a second pitch, wherein the first pitch and second pitch are such that a combined pitch of the first and second features is constant irrespective of the presence of pitch walk in the plurality of features.

Abstract: A method includes selecting a group of wafers, each of the wafers having a resist pattern; selecting a group of fields for each of the wafers; selecting one or more points on each of the fields; measuring overlay errors on the resist pattern at locations associated with the one or more points selected on the respective wafers; and generating a combined overlay correction map based on measurements of the overlay errors on the wafers. At least one of the selecting of the group of wafers, the selecting of the group of fields, and the selecting of the one or more points is based on a computer-generated model.

Abstract: A method of optimizing a power consumption of an integrated circuit design, includes dividing the integrated circuit design into N circuit partitions, supplying each circuit partition to a different one of N computer systems each associated with a different one of the N circuit partitions, training each of the N computer systems to reduce the power consumption of its associated circuit partition thereby to generate N training data, storing the N training data in a database, and applying the N training data to the integrated circuit design thereby to reduce the consumption of the integrated circuit design.

Abstract: A method for fabricating a semiconductor structure is provided. The method includes assigning a set of parameter values to a set of size parameters of a unit cell of the integrated circuit in a unit cell schematic of the unit cell according to a predetermined criterion, wherein the unit cell characterized by the set of parameter values has a circuit characteristic meeting the predetermined criterion; generating a unit cell layout of the unit cell according to the unit cell schematic; generating a circuit layout comprising a plurality of replicas of the unit cell layout, the replicas of the unit cell layout being arranged in correspondence with circuit blocks in a circuit floorplan of the integrated circuit, respectively; and fabricating the integrated circuit according to the circuit layout.

Abstract: Example systems and methods are disclosed for estimating power consumption by a clock tree in a register-transfer level (RTL) circuit design based on a previously generated reference gate-level circuit design. A plurality of regions within the clock tree structure of the reference gate-level circuit design are identified, where the plurality of regions are demarcated by one or more clock gating structures. A region-based clock model is generated that includes at least one clock constraint model for each identified region. The region-based clock model is used to synthesize the clock tree in the RTL circuit design for estimating power consumption.

Abstract: A method for repairing logic design includes inserting primary logic gates in a primary logic design path of a logic chip. The method also includes inserting alternative logic gates in an alternate logic design path of the logic chip. The alternate logic design path and the primary logic design path are coupled to multiple fuses. The potentially defective design is repaired by selecting between the alternate logic design path and the primary logic design path with the fuses when the logic design is defective.

Abstract: A semiconductor cell structure includes four transistors, two gate-strips, four pairs of conductive segments, and a plurality of horizontal routing lines. Each of the two gate-strips intersects a first-type active zone and a second-type active zone. A first conductive segment is configured to have a first supply voltage. A second conductive segment is configured to have a second supply voltage. The first gate-strip is conductively connected to the second conductive segment. Each of the horizontal routing lines intersects one or more conductive segments over one or more corresponding intersections while conductively isolated from the one or more conductive segments at each of the one or more corresponding intersections.

Abstract: The technology disclosed generates resistor values for networks with more than four terminals. In this case, all resistors in the network can be found by updating point-to-point (P2P) values as the network is reduced. To find the resistor value RAB between two terminals, A and B, the other terminals are effectively shorted together, reducing the network. Such reduction does not affect RAB. The point-to-point (P2P) resistance values are recalculated as other terminals are shorted. Once reduced to four terminals, the P2P resistance values are sufficient to determine RAB. Given six P2P resistance values, it generates the six resistor values required for the resistor network connecting the four terminals.

Abstract: Efficiency of electronic design automation is increased by accessing a data structure characterizing a hierarchical integrated circuit design including sub-blocks each with a plurality of ports. For each given one of the ports of each of the sub-blocks, obtain a wire specification for a corresponding net connected to the given one of the ports in the design, and based on the wire specification, consult a technology-specific lookup table to determine at least one of a corresponding default driving cell and default electrical model for an external wire coupling one of the default driving cell and an actual driving cell to the given one of the ports. Optimize each of the sub-blocks out-of-context based on the at least one of default driving cells and default electrical models; verify in-context closure for the optimized sub-blocks; and, responsive to the in-context closure, update the data structure to reflect the optimized sub-blocks.

Abstract: A non-volatile dual-in-line memory module (NVDIMM) with a parallel architecture is described. It enables parallel access to on-board nonvolatile memory (NVM) to improve storage throughput and to alleviate layout design constraints.

Abstract: Systems and methods are provided for predicting static voltage (SIR) drop violations in a clock-tree synthesis (CTS) layout before routing is performed on the CTS layout. A static voltage (SIR) drop violation prediction system includes SIR drop violation prediction circuitry. The SIR drop violation prediction circuitry receives CTS data associated with a CTS layout. The SIR drop violation prediction circuitry inspects the CTS layout data associated with the CTS layout, and the CTS layout data may include data associated with a plurality of regions of the CTS layout, which may be inspected on a region-by-region basis. The SIR drop violation prediction circuitry predicts whether one or more SIR drop violations would be present in the CTS layout due to a subsequent routing of the CTS layout.

Abstract: A method and a device for generating boundary-scan interconnection lines are disclosed. In the method, the boundary scan test model is established according to boundary scan components and intermediate components on least one test card and a unit under test (UUT) board, and connection relationships therebetween; the boundary scan nets of the boundary scan test model are constructed; the boundary scan paths of each boundary scan net are generated, and a path establishment condition of each boundary scan path is obtained; and the boundary scan paths are filtered and integrated, and the filtered and integrated boundary scan paths are divided according to the path establishment conditions of filtered and integrated boundary scan paths, into subtests which each has at least one boundary-scan interconnection line. As a result, the accuracy and high coverage of a path search operation can be guaranteed.