Abstract: A system for charging an electrical energy store by means of a converter. The converter monitors an electrical connection between the converter and the electrical energy store. If an interruption of the electrical connection between the converter and the electrical energy store is detected, for example, the opening of a circuit breaker between the electrical energy store and the converter, the further provision of electrical power for charging the electrical energy store through is immediately prevented by the converter.

Abstract: A system and method for adding interface protection to an electronic design using parameters. The electronic design and interface protection scheme are defined as parameters. An interface protection model creates interface protection implementation parameters that describe the implementation details of the interface protection. A hardware description model uses the electronic design parameters and the interface protection implementation parameters to create a hardware description. The interface protection scheme can be a built-in protection scheme, a user defined scheme, a scheme that includes place holders that the user may define later, and a combination of the preceding. The interface protection scheme may contain components to help with the retiming of the description of hardware.

Abstract: A method includes determining a cell loading of a cell in an integrated circuit (IC) layout diagram. Based on the determined cell loading, a power parameter associated with the cell is determined. In response to the determined power parameter exceeding a design criterion, at least one of altering a placement of the cell in the IC layout diagram or modifying a power delivery path to the cell is performed. At least one of the determining the cell loading, the determining the power parameter, the altering the placement of the cell, or the modifying the power delivery path is executed by a processor.

Abstract: A clock deadlock detecting system includes a memory and a processor. The memory is configured to store at least one computer program. The processor is configured to execute the at least one computer program to perform following operations: extracting hierarchy information of a plurality of integrated clock gating (ICG) cells, in which the hierarchy information is a description of a circuit structure of the ICG cells; generating at least one checking property according to integrated circuit design information and the hierarchy information; determining whether the ICG cells satisfy the at least one checking property according to the integrated circuit design information and a formal method to determine whether the ICG cells is expected to fall into at least one clock deadlock state, so as to generate a determination result; and modifying the integrated circuit design information according to the determination result.

Abstract: A method that includes disabling circuit paths in a circuit under test during transition fault testing (TFT) of valid timing paths of the circuit under test. The method then tests the circuit paths at slower clock speeds than the clock speed of the valid timing paths during TFT of the circuit paths. Finally, the method tests the circuit paths and the valid timing paths to facilitate testing of the circuit under test.

Abstract: Determining on-chip memory access patterns can include modifying a circuit design to include a profiler circuit for a random-access memory (RAM) of the circuit design, wherein the profiler circuit is configured to monitor an address bus of the RAM, and modifying the circuit design to include a debug circuit connected to the profiler circuit. Usage data for the RAM can be generated by detecting, using the profiler circuit, addresses of the RAM accessed during a test of the circuit design, as implemented in an integrated circuit. The usage data for the RAM can be output using the debug circuit.

Abstract: Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

Abstract: In certain aspects of the disclosure, a system includes an isolation device coupled between a first circuit in a first power domain and a second circuit in a second power domain. The system also includes a second power source coupled to a power distribution network, wherein the power distribution network is configured to distribute power from a first power source to the second power domain. The system further includes a failure detector having an input coupled to a node on the power distribution network located upstream of the second power source, and an output coupled to the isolation device, wherein the failure detector is configured to sense a voltage at the node, to detect a power loss of the first power source based on the sensed voltage, and to enable the isolation device in response to detection of the power loss.

Abstract: A function equivalence check method includes receiving a cell list, receiving an analog constraint of a cell in the cell list, generating the full-coverage input stimuli according to the analog constraint, performing a behavioral-level simulation using the full-coverage input stimuli and according to the behavioral code to generate a behavioral-level simulation result, performing a circuit-level simulation using the full-coverage input stimuli and according to the circuit-level netlist to generate a circuit-level simulation result, and comparing the behavioral-level simulation result and the circuit-level simulation result to generate a comparison report for an analog value auto-comparison.

Abstract: To solve the technical problem of the incapacity to perform a quantitative matching design of residual compressive stress in the process of prior structural cold working-residual compressive stress design, the invention provides a method of structural cold working-residual compressive stress distribution quantitative matching design, characterized by treating the fatigue strength of a mechanical structure and parts as a field, and matching a structural stress field and a fatigue strength field organically, to quantitatively match the residual compressive stress in conjunction with characteristics of the cold working process.

Abstract: A simulation apparatus includes: a factor amount converting information storage unit in which factor amount converting information, which is information indicating correspondence between low-fidelity information and high-fidelity information, is stored; a writing pattern information storage unit in which writing pattern information is stored; an ADI simulation unit that performs an ADI simulation using one or more evaluation points, for a writing pattern indicated by the writing pattern information, thereby acquiring one or more factor amounts; a converting unit that acquires high-fidelity information, which is one or more factor amounts, corresponding to the low-fidelity information, which is one or more factor amounts, using the factor amount converting information; and an etching simulation unit that performs an etching simulation using the one or more factor amounts acquired by the converting unit.

Abstract: A processing method for applying an analog dynamic circuit to a digital testing tool includes the following steps. In a step (a), a transistor-level analog dynamic circuit is provided. In a step (b), plural equivalent models are designed according to operations of plural transistors in the transistor-level analog dynamic circuit. In a step (c), a substitution operation is performed to substitute the equivalent models for dynamic logic elements in the transistor-level analog dynamic circuit. Consequently, a gate-level substitution circuit is produced. In a step (d), the gate-level substitution circuit is imported into a digital testing tool. Consequently, a test pattern is generated. In a step (e), the transistor-level analog dynamic circuit is tested according to the test pattern.

Abstract: A formal verification EDA application can be configured to receive a circuit design of an IC chip, the circuit design of the IC chip including a list of properties for the IC chip. The list of properties includes a list of covers for the IC chip. The formal verification engine can also execute a formal verification of the IC chip. Results of the formal verification identifies a subset of covers of the list of covers that are unreachable. The formal verification engine can further execute a root cause search for a selected cover in the subset of covers that are unreachable. The root cause search selectively adds and removes cutpoints to signals in the circuit design to identify a root cause for the selected cover being unreachable. The root cause comprises a signal in the circuit design that is upstream from the selected cover.

Abstract: A method for testing a design is provided. The method includes generating a sequence of bits, mapping the sequence of bits to a combination, and generating an enable signal based on the combination. The enable signal enables an asynchronous signal in the design. The method also includes driving an element of the design based on the enabled asynchronous signal.

Abstract: A system for charging a battery carried by a vehicle may include a charging box for coupling to a vehicle chassis and including interface electrical contacts electrically coupled to the battery. The system may also include a charge coupler including coupler electrical contacts for electrically coupling to the interface electrical contacts from under the vehicle and configured to be coupled to an electrical power supply. The charging box may include an interface activation surface, and the charge coupler may include a housing for enclosing the coupler electrical contacts and including a base for supporting the coupler electrical contacts, a coupler activation surface opposite the base, an opening, and a door configured to open the opening to expose the coupler electrical contacts as the interface activation surface contacts the coupler activation surface and moves the coupler activation surface toward the base.

Abstract: Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform.

Abstract: According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including: a first scan chain and a second scan chain; a clock generator; and a test control circuit. The first scan chain includes: a first flip-flop having a first scan data input terminal and a first output terminal; and a first multiplexer. The first multiplexer is configured to electrically couple the first scan data input terminal to the first output terminal based on a first signal received from the test control circuit to form a first closed loop. The second scan chain includes a second flip-flop having a second scan data input terminal and a third output terminal that is not coupled to the second scan data input terminal.

Abstract: A charging inlet includes a power terminal, a holder member, and a thermal sensor. The power terminal is configured to releasably engage a mating contact of an external power source. The holder member is proximate to the power terminal, and has an electrically insulative material. The holder member defines at least a portion of a pocket that is fully enclosed. The thermal sensor is disposed within the pocket for monitoring a temperature of the power terminal.

Abstract: This application discloses a computing system implementing an automatic test pattern generation tool can generate test patterns to apply to a reversible scan chain in an integrated circuit. The reversible scan chain can be configured to serially load and unload the test patterns in multiple directions to generate test responses. The computing system can implement a defect diagnosis tool to detect a presence of a suspected defect associated with the reversible scan chain based on the test responses, identify which of the multiple directions used to load and unload the test patterns corresponds to the suspected defect in the reversible scan chain based on the test responses, and determine a portion of the integrated circuit to inspect for a manufacturing fault corresponding to the suspected defect based, at least in part, on the identification of which of the multiple directions corresponds to the suspected defect in the reversible scan chain.

Abstract: A battery charging method and apparatus are provided. The battery charging apparatus receives a desired charging time of a battery, generates charging currents of charging steps to charge the battery based on the desired charging time, acquires a charging limit condition including an internal state condition and a maximum charging time for each of the charging steps based on the desired charging time and an electrochemical model of the battery, and generates a charging profile including the charging currents and charging times of the charging currents based on the charging limit condition.