Patents Examined by Phat X. Cao
  • Patent number: 10692995
    Abstract: The present invention provides an insulated-gate bipolar transistor (IGBT) structure and a method for manufacturing the same. The structure is a planar IGBT structure, and is characterized by an ultra-thin channel and buried oxide located below the channel. The structure can provide the theoretically lowest on-state voltage drop.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: June 23, 2020
    Inventor: Ka Kit Wong
  • Patent number: 10686064
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: June 16, 2020
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Yamamoto, Tetsuya Fujiwara, Minoru Akutsu, Ken Nakahara, Norikazu Ito
  • Patent number: 10686062
    Abstract: This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.
    Type: Grant
    Filed: May 11, 2013
    Date of Patent: June 16, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Madhur Bobde, Anup Bhalla
  • Patent number: 10686081
    Abstract: This application relates to the technical field of semiconductors, and discloses a semiconductor device, an MOS capacitor, and manufacturing methods therefor.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: June 16, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 10679960
    Abstract: A heat and shock resistant integrated circuit (IC) of the present invention includes a base material, a metal layer disposed on the base material, a silicon die disposed on the metal layer, additive material disposed on the base material, gas filled filler material disposed between the additive material and the silicon die, and first traces electrically connecting the silicon die to the additive material. Packing of the integrated circuit provides exceptional thermal stress relief and impact protection of circuitry within the packaging.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 9, 2020
    Assignee: Hall Labs LLC
    Inventors: David R. Hall, Marshall Soares, Derek Maxwell, Richard Rea
  • Patent number: 10680192
    Abstract: Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 9, 2020
    Assignee: Corning Incorporated
    Inventors: Robert Alan Bellman, Mingqian He, Timothy Edward Myers, Weijun Niu, David Neal Schissel, Kristi Lynn Simonton, Arthur Lawrence Wallace
  • Patent number: 10680102
    Abstract: A method of forming a semiconductor device that includes forming at least two semiconductor fin structures having sidewalls with {100} crystalline planes that is present atop a supporting substrate; and epitaxially growing a source/drain region in a lateral direction from the sidewalls of each fin structure. The second source/drain regions have substantially planar sidewalls. A metal wrap around electrode is formed on an upper surface and the substantially planar sidewalls of the source/drain regions. Air gaps are formed between the source/drain regions of the at least two semiconductor fin structures.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 9, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Choonghyun Lee, Kangguo Cheng, Juntao Li, Shogo Mochizuki
  • Patent number: 10672741
    Abstract: In some embodiments, a device includes a thermal-electrical-mechanical (TEM) chip having a functional circuit, a first die attached to a first side of the TEM chip, and a first via on the first side of the TEM chip and adjacent to the first die, the first via being electrically coupled to the TEM chip. The device also includes a first molding layer surrounding the TEM chip, the first die and the first via, where an upper surface of the first die and an upper surface of the first via are level with an upper surface of the first molding layer. The device further includes a first redistribution layer over the upper surface of the first molding layer and electrically coupled to the first via and the first die.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: June 2, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Hsien Huang, Yueh-Ting Lin, Wei-Yu Chen, An-Jhih Su
  • Patent number: 10672638
    Abstract: A chip pickup system is provided. The chip pickup system includes a detector for detecting a position of an irregular semiconductor chip on a holder. The holder holding plural semiconductor chips in predetermined positions on the holder. The irregular semiconductor chip is out of the predetermined positions. The system further includes a pickup tool for picking up the irregular semiconductor chip at least on the basis of information on the position of the irregular semiconductor chip detected by the detector.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: June 2, 2020
    Assignee: International Business Machines Corporation
    Inventors: Akihiro Horibe, Kuniaki Sueoka
  • Patent number: 10658184
    Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Tien Shen, Chi-Cheng Hung, Chin-Hsiang Lin, Chien-Wei Wang, Ching-Yu Chang, Chih-Yuan Ting, Kuei-Shun Chen, Ru-Gun Liu, Wei-Liang Lin, Ya Hui Chang, Yuan-Hsiang Lung, Yen-Ming Chen, Yung-Sung Yen
  • Patent number: 10643889
    Abstract: A method of improving selectivity of a metal in a selective deposition process. A pre-treatment process for the metal modifies the metal surface, and includes first reducing the metal to remove organic contamination from the metal followed by oxidation of the metal to allow a monolayer of a metal oxide to grow on the surface. This modification of the metal allows inhibitor molecules to adsorb on the metal oxide monolayer to improve selectivity.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: May 5, 2020
    Assignee: Lam Rasearch Corporation
    Inventors: Dennis Hausmann, Elham Mohimi, Pengyi Zhang, Paul C. Lemaire, Kashish Sharma, Alexander R. Fox, Nagraj Shankar, Kapu Sirish Reddy, David Charles Smith
  • Patent number: 10644120
    Abstract: A thin film transistor is disclosed, comprising a first, second and third electrode. The first and second electrodes are arranged in a same layer and insulated from each other. The third electrode is arranged below and insulated from the first and second electrodes. The first electrode comprises at least one first conducting part. The second electrode comprises second conducting parts, each of which is arranged adjacent with each first conducting part. The third electrode is provided with an opening part at least partially overlapping with the first or second conducting part. If the first or second conducting part is subject to a channel defect due to short circuit, the first or second conducting part is cut off at an overlapping position with the opening part, to repair the channel defect without affecting the third electrode. A GOA circuit, a display substrate and a display device are further disclosed.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: May 5, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Wei He, Xinjie Zhang, Wenlong Xiao, Siquan Wu
  • Patent number: 10644061
    Abstract: A photodetector-array and fabrication method thereof are disclosed. The photodetector-array includes a first and second semiconductor structures having respective active regions defining respective pluralities of active photodetectors and active readout integrated circuit pixels (RICPs) electronically connectable to one another respectively. The first and second semiconductor structures are made with different semiconductor materials/compositions having different first and second coefficients of thermal expansion (CTEs) respectively. The pitch distances of the active photodetectors and the pitch distances of the respective active RICPs are configured in accordance with the difference between the first and second CTEs, such that at high temperatures, at which electrical coupling between the first and second semiconductor structures is performed, the electric contacts of the active photodetectors and of their respective RICPs overlap.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: May 5, 2020
    Assignee: Semi Conductor Devices—an Elbit Systems-Rafael Partnership
    Inventors: Yoram Karni, Inna Lukomsky, Eran Avnon
  • Patent number: 10636936
    Abstract: A micro-electro-mechanical systems (MEMS) array system is configured to apply suction forces for the manipulation of objects. The MEMS system includes includes a two-dimensional MEMS array of a plurality of individual MEMS elements. Each MEMS element comprises: a casing structure; a flexible membrane attached to the casing structure; and an electrode structure, wherein a voltage applied to the electrode structure actuates the MEMS element to cause the flexible membrane to flex relative to the casing structure. The flexible membrane and the casing structure define a gap into which the flexible membrane may flex, and a foot extends from the flexible membrane in a direction away from the casing structure, wherein the foot and the flexible membrane define a clearance region on an opposite side of the flexible membrane from the gap. When the MEMS element interacts with an object to be manipulated the foot spaces the membrane apart from the object.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 28, 2020
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hywel Hopkin, Nathan James Smith, Andrew Kay
  • Patent number: 10636672
    Abstract: A method for manufacturing an interconnect structure includes providing a metal interconnect layer, forming a first dielectric layer on the metal interconnect layer, forming a fluorocarbon layer on the first dielectric layer, forming a second dielectric layer on the fluorocarbon layer, and performing an etch process on the second dielectric layer using the fluorocarbon layer as an etch stop mask to form an opening. The interconnect structure thus formed has an improved uniformity and reduced parasitic capacitance.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: April 28, 2020
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Ming Zhou
  • Patent number: 10615030
    Abstract: An exemplary method of preparing nitrogen-doped graphene whereby it is possible to synthesize graphene having an improved surface coverage and a uniform single layer, and to prepare high quality graphene in a large area. In addition, an aromatic compound containing nitrogen can be used as a carbon source and nitrogen-doped graphene can be thus synthesized as nitrogen doped in the synthesis process. It is possible to control the electrical properties of graphene depending on the nitrogen doping.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 7, 2020
    Assignee: GWANGJU INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Moon Ho Ham, Myung Woo Son
  • Patent number: 10608086
    Abstract: The present invention provides a semiconductor structure, the semiconductor structure includes a substrate, at least one active area is defined on the substrate, a buried word line is disposed in the substrate, a source/drain region disposed beside the buried word line, a diffusion barrier region, disposed at the top of the source/drain region, the diffusion barrier region comprises a plurality of doping atoms selected from the group consisting of carbon atoms, nitrogen atoms, germanium atoms, oxygen atoms, helium atoms and xenon atoms, a dielectric layer disposed on the substrate, and a contact structure disposed in the dielectric layer, and electrically connected to the source/drain region.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: March 31, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan
  • Patent number: 10593796
    Abstract: A transistor includes a substrate of a first conductivity type. An epitaxial layer of the first conductivity type is formed at a top surface of the substrate. A first region of the first conductivity type is formed as a well in the epitaxial layer. A second region of a second conductivity type is formed as a well in the epitaxial layer adjacent to the first region and the second conductivity type is opposite of the first conductivity type. A third region of the second conductivity type is formed in the first region and a portion of the first region forms a channel region between the third region and the second region. An emitter region of the first conductivity type is formed in the second region. A gate dielectric is formed over the channel region, and a gate electrode is formed on gate dielectric with the gate electrode overlapping at least a portion of second region and the third region.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: March 17, 2020
    Assignee: NXP USA, INC.
    Inventors: Zihao M. Gao, Christopher Paul Dragon, Walter Sherrard Wright
  • Patent number: 10593848
    Abstract: A light-emitting element package according to one embodiment includes first and second lead frames electrically separated from each other; a package body including a slope configured to define a cavity along with at least one of the first or second lead frame; and at least one element unit disposed in an element area of at least one of the first or second lead frame, the element unit including a light-emitting element and a protective element, wherein the package body is disposed between the protective element and the light-emitting element.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: March 17, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Dong Hyun Yu, Bong Kul Min
  • Patent number: 10573667
    Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: February 25, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hisao Ikeda, Kouhei Toyotaka, Hideaki Shishido, Hiroyuki Miyake, Kohei Yokoyama, Yasuhiro Jinbo, Yoshitaka Dozen, Takaaki Nagata, Shinichi Hirasa