Patents Examined by Phat X. Cao
  • Patent number: 11515229
    Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 29, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Lai, Chien-Chia Chiu, Chen-Hua Yu, Der-Chyang Yeh, Cheng-Hsien Hsieh, Li-Han Hsu, Tsung-Shu Lin, Wei-Cheng Wu, Yu-Chen Hsu
  • Patent number: 11515311
    Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Venkata Naveen Kumar Neelapala, Deepak Chandra Pandey, Naveen Kaushik
  • Patent number: 11515321
    Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: November 29, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Changhan Kim
  • Patent number: 11508693
    Abstract: A memory device includes a first semiconductor wafer portion including two or more adjacent quasi-volatile memory circuits formed on a common semiconductor substrate where each quasi-volatile memory circuit being isolated from an adjacent quasi-volatile memory circuit by scribe lines; and a second semiconductor wafer portion including at least one memory controller circuit formed on a semiconductor substrate. The memory controller circuit includes logic circuits and interface circuits. The memory controller circuit is interconnected to the two or more adjacent quasi-volatile memory circuits of the first semiconductor wafer portion through interconnect structures and the memory controller circuit operates the two or more quasi-volatile memory circuits as one or more quasi-volatile memories.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: November 22, 2022
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Robert D. Norman, Richard S. Chernicoff, Eli Harari
  • Patent number: 11502035
    Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Su-Jen Sung
  • Patent number: 11486562
    Abstract: Systems for apparatuses formed of light emitting devices. Solutions for controlling the off-state appearance of lighting system designs is disclosed. Thermochromic materials are selected in accordance with a desired off-state of an LED device. The thermochromic materials are applied to a structure that is in a light path of light emitted by the LED device. In the off-state the LED device produces a desired off-state colored appearance. When the LED device is in the on-state, the thermochromic materials heat up and become more and more transparent. The light emitted from the device in its on-state does not suffer from color shifting due to the presence of the thermochromic materials. Furthermore, light emitted from the LED device in its on-state does not suffer from attenuation due to the presence of the thermochromic materials. Techniques to select and position thermochromic materials in or around LED apparatuses are presented.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 1, 2022
    Assignee: Lumileds LLC
    Inventors: Hisashi Masui, Oleg Shchekin, Ken Shimizu, Marcel Bohmer, Frank Jin, Jyoti Bhardwaj
  • Patent number: 11489042
    Abstract: A semiconductor device is provided.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: November 1, 2022
    Assignee: POWER MASTER SEMICONDUCTOR CO., LTD.
    Inventors: Jaegil Lee, Sangtae Han
  • Patent number: 11469293
    Abstract: A display device including: a substrate including a display area, a peripheral area, and a pad area; a first main voltage line in the peripheral area, and a first connector extending from the first main voltage line to the pad area; and a second main voltage line in the peripheral area, and a second connector extending from the second main voltage line to the pad area, wherein each of the first connector and the second connector includes a first and second layer overlapping each other with a first insulating layer therebetween, the first insulating layer is in the display area and the peripheral area, the peripheral area includes an open area exposing the first and second connector and surrounding the display area, and the first insulating layer includes slits between the first and second connector and extending from an end of the first insulating layer toward the display area.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: October 11, 2022
    Inventors: Ilgoo Youn, Jaewon Kim, Hyunae Park, Hyungjun Park, Seungwoo Sung, Junyong An, Nuree Um, Youngsoo Yoon, Jieun Lee, Seunghan Jo
  • Patent number: 11469207
    Abstract: A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to an opposite side of the first set of stacked semiconductor devices; and (5) a temperature adjusting component at the second side and aligned with the second set of stacked semiconductor devices. The temperature adjusting component is positioned to absorb the thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: October 11, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Sui Chi Huang
  • Patent number: 11456385
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: September 27, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 11443994
    Abstract: The present application provides an electronic package having an optoelectronic component and a laser component disposed on a packaging unit, with the optoelectronic component and the laser component being separated from each other. Since the laser component and the optoelectronic component are separated from each other, the electronic package has a reduced fabrication difficulty and a high yield rate. A method for fabricating the electronic package and an electronic packaging module having the electronic package are also provided.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 13, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Jin-Wei You, Cheng-Kai Chang
  • Patent number: 11444223
    Abstract: A light emitting device including at least one first light emitting unit including an ultraviolet or violet light emitting diode chip and a first wavelength converter, at least one second light emitting unit including an ultraviolet or violet light emitting diode chip and a second wavelength converter, and at least one third light emitting unit including an ultraviolet or violet light emitting diode chip and a third wavelength converter, in which color coordinates of the first light emitting unit, the second light emitting unit, and the third light emitting unit define a triangular region in a CIE-1931 coordinate system, the triangular region including at least a portion of the Plankian locus, and a maximum color temperature of the Plankian locus included in the triangular region is 5000K or higher, and a minimum color temperature of the Plankian locus included in the triangular region is 3000K or lower.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 13, 2022
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Bo Yong Han
  • Patent number: 11437439
    Abstract: Display devices are disclosed herein. In one embodiment, the display device includes a plastic substrate comprising a display area and a non-display area, and a data pad portion disposed on one side of the non-display area, with a flexible circuit board bonded thereto, the display area including a plurality of subpixels positioned on the display area, each subpixel including an organic light-emitting diode that includes an organic layer, wherein the organic layer extends continuously from one side of the display area to the other side of the display area and is arranged in a plurality of lines that are spaced apart from one another and disposed parallel to the data pad portion.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 6, 2022
    Assignee: LG Display Co., Ltd.
    Inventors: Eunah Kim, Sangcheon Youn, Saemleenuri Lee
  • Patent number: 11437416
    Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a first photodetector and a second photodetector each disposed within a semiconductor substrate. An isolation structure extends from a front-side surface of the semiconductor substrate to a back-side surface of the semiconductor substrate. The front-side surface is opposite the back-side surface and the isolation structure is laterally between the first and second photodetectors. A readout transistor is disposed on the front-side surface of the semiconductor substrate. A first side of the readout transistor overlies the first photodetector and a second side of the readout transistor overlies the second photodetector. The first side is opposite the second side and the readout transistor continuously extends over the isolation structure.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Seiji Takahashi
  • Patent number: 11437308
    Abstract: A packaging glass substrate for semiconductor includes a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias penetrating through the glass substrate in a thickness direction, wherein a plain line is a line linking places where the core vias are not formed, a via line is a line linking places where the core vias are formed, a stress difference value (P) is a value according to Equation (1), and the stress difference value (P) is 1.5 MPa or less, Equation (1): P=Vp?Np where P is a stress difference value measured at the same glass substrate, Vp is a difference between the maximum value and the minimum value of stress measured at the via line, and Np is a difference between the maximum value and the minimum value of stress measured at the plain line.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: September 6, 2022
    Assignee: ABSOLICS INC.
    Inventors: Youngho Rho, Sungjin Kim, Jincheol Kim
  • Patent number: 11430763
    Abstract: A semiconductor package includes a plurality of stack modules which are vertically stacked. Each of the stack modules includes an interposing bridge, a semiconductor dies, and redistribution lines. The stack modules are provided by rotating each of the stack modules by different rotation angles corresponding to multiples of a reference angle and by vertically stacking the rotated stack modules. The interposing bridge includes a plurality of sets of through vias, and each set of through vias includes through vias arrayed in a plurality of columns. The plurality of sets of through vias are disposed in respective ones of divided regions of the interposing bridge. If the plurality of sets of through vias are rotated by the reference angle, then the rotated through vias overlap with the plurality of sets of through vias which are originally located. The redistribution lines connect the semiconductor dies to the plurality of sets of through vias.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 30, 2022
    Assignee: SK hynix Inc.
    Inventors: Bok Kyu Choi, Kyoung Tae Eun
  • Patent number: 11430932
    Abstract: The present disclosure relates to a driving backplane, a micro-LED display panel and a micro-LED display device. The driving backplane, includes a plurality of pixel units arranged in an array, each of the pixel units comprising: an anode lead; a cathode lead at a side of the anode lead; and at least two pairs of electrodes, each pair of electrodes of the at least two pairs of electrodes including an anode and a cathode oppositely disposed, the anode being electrically connected to the anode lead, and the cathode being electrically connected to the cathode lead. In the course of using the foregoing driving backplane of the micro-LED display panel, it is only necessary to solder an LED chip on one pair of electrodes of the at least two pairs of electrodes.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: August 30, 2022
    Assignee: CHENGDU VISTAR OPTOELECTRONICS CO., LTD.
    Inventors: Rubo Xing, Dong Wei, Xiaolong Yang, Qi Shan
  • Patent number: 11424392
    Abstract: A manufacturing method of a light emitting diode apparatus is provided. This method includes forming a light emitting diode on the substrate, forming a light leakage preventing layer to surround the side surface of the light emitting diode, etching a region corresponding to the light emitting diode in the substrate, and bonding a wavelength converting material to a lower portion of the light emitting diode in the etched region, in which the wavelength converting material includes a semiconductor layer including a quantum well layer.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-hee Kang, Ji-Hoon Kang, Seong-woo Cho
  • Patent number: 11424202
    Abstract: A semiconductor device includes a landing pad, a first insulating pattern in contact with a lower portion of a side surface of the landing pad, a pad oxide layer having a lateral portion disposed on a portion of an upper surface of the landing pad and a vertical portion in contact with an upper portion of the side surface of the landing pad, a second insulating pattern in contact with an upper surface of the first insulating pattern and covering the first insulating pattern and the pad oxide layer, and a lower electrode that vertically passes through the second insulating pattern and is in contact with a portion of the upper surface and an upper portion of a side surface of the landing pad.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: August 23, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bowo Choi, Youngtak Kim, Sangjine Park, Suji Kim, Jaeuk Shin, Hyunjung Lee, Jihun Cheon
  • Patent number: 11387239
    Abstract: A transistor structure of a semiconductor memory device comprises: an active area having a plurality of trenches and a substrate surface, the trenches having openings oriented toward the substrate surface; a plurality of gate structures embedded in the trenches, wherein the substrate surface comprises source regions located on outer sides of the gate structures and a drain region located between the gate structures; node contacts each disposed on one of the source regions; a bit line contact disposed on the drain region and connectable to a bit line, the node contacts sharing the bit line contact through adjacent gate structures, wherein the drain region comprises a first ion implantation layer extending inwardly from the bit line contact, each of the source regions comprising a second ion implantation layer extending inwardly from a corresponding node contact, the first ion implantation layer being deeper than the second ion implantation layer.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: July 12, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventor: Chih Cheng Liu