Abstract: A superstrate can comprise a superstrate blank and a coating overlying an outer surface of the superstrate blank. The superstrate blank can comprises a central region and a tapered edge region, wherein the tapered edge region has an average taper angle of not greater than 20 degrees relative to a length direction of the superstrate blank. In one embodiment, the coating of the superstrate can be applied by spin coating and may have an edge bead below a plane of the coating surface within the central region.

Abstract: A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.

Abstract: A semiconductor package includes a redistribution substrate including a first redistribution layer; a semiconductor chip having a connection pad connected to the first redistribution layer; a vertical connection conductor electrically connected to the connection pad by the first redistribution layer; a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor; an encapsulant filling the first and second through-holes; and a redistribution member including a second redistribution layer. The vertical connection conductor and the core member include a same material. A width of a lower surface of the vertical connection conductor is wider than that of an upper surface thereof, a width of a lower end of the first through-hole is narrower than that of an upper end thereof, and a width of a lower end of the second through-hole is narrower than that of an upper end thereof.

Abstract: An electronic device package and a method for manufacturing the same are provided. The electronic device package includes a substrate, a conductive trace, a passivation layer and an upper wiring. The conductive trace is disposed over the substrate. The conductive trace includes a body portion disposed on the substrate, and a cap portion disposed on the body portion, and the cap portion is wider than the body portion. The passivation layer covers the conductive trace. The upper wiring is disposed on the passivation layer and electrically connected to the cap portion of the conductive trace through an opening of the passivation layer.

Abstract: A method generating a layout diagram includes: arranging the layout diagram into rows; configuring one or more of the rows as combination rows, the combination-row-configuring including relative to a second direction substantially perpendicular to the first direction, setting a height of each of the one or more combination rows to be substantially equal to a sum of a first height of a first cell and a second height of a second cell, the first cell being different than the second cell, and the first height being different than the second height; and populating each of the one or more combination rows including: stacking a first instance of the first cell on a first instance of the second cell, or stacking a second instance of the second cell on a second instance of the first cell.

Abstract: Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chiplet disposed on the common substrate. The first IC chiplet includes at least one processing element. A communications fabric switchably couples to the at least one processing element. A peripheral gearbox chiplet (PGC) includes a first port having a second memory-agnostic interface coupled to the first memory-agnostic interface of the first IC chiplet. The PGC includes a second port having a memory interface of a first type and interface conversion circuitry disposed between the second memory-agnostic interface and the memory interface of the first type.

Abstract: An approach to forming a semiconductor device where the semiconductor device includes a first power rail with one or more vertically stacked contact vias connecting to the first power rail to a portion of a first de-coupling capacitor. The semiconductor device includes the first de-coupling capacitor in a first portion of a semiconductor substrate in a first gate cut trench.

Abstract: A method includes forming a patterned mask comprising a first opening, plating a conductive feature in the first opening, depositing a passivation layer on a sidewall and a top surface of the conductive feature, and patterning the passivation layer to form a second opening in the passivation layer. The passivation layer has sidewalls facing the second opening. A planarization layer is dispensed on the passivation layer. The planarization layer is patterned to form a third opening. After the planarization layer is patterned, a portion of the planarization layer is located in the second opening and covers the sidewalls of the passivation layer. An Under-Bump Metallurgy (UBM) is formed to extend into the third opening.

Abstract: A hybrid via interconnect structure includes a first metal filling at least partially surrounded by a first barrier metal layer, a second metal filling at least partially surrounded by a second barrier metal layer, and a hybrid via formed between the first metal filling and the second metal filling. The hybrid via provides an electrical connection between the first metal filling and the second metal filling and is formed of a different material than the first metal filling, the second metal filling, the first barrier metal layer, and the second barrier metal layer. The hybrid via interconnect structure can be formed during the back end of line (BEOL) portion of an integrated circuit (IC) fabrication process to provide reduced interconnect resistance and improved ease of fabrication.

Abstract: An array of heat-sinked power semiconductors that includes a power semiconductor and a heat sink. The power semiconductor has a power semiconductor die, a plurality of first terminals and a second terminal. The power semiconductor die has a plurality of semiconductor terminals. Each of the first terminals is electrically coupled to an associated one of the semiconductor terminals. The second terminal is a surface mount terminal and is electrically coupled to one of the first terminals. The heat sink has a heat sink body and a plurality of fins. The heat sink body has a base and an exterior surface. The base is fixedly coupled directly to the surface mount terminal. The exterior surface has a fin mount portion to which the fins extend. At least a portion of the fin-mount portion is oriented non-parallel to base.

Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.

Abstract: A standard cell comprises a first active region and a first power rail, the first active region and the first power rail disposed in a first MOS region; a second active region and a second power rail, the second active region and the second power rail disposed in a second MOS region; and a gate electrode extending to cross the first and second active regions and the first and second power rails in a first direction, wherein the first power rail is disposed closer to a boundary between the first MOS region and the second MOS region than to a first side of the first MOS region opposite the boundary, and wherein the second power rail is disposed closer to the boundary between the first MOS region and the second MOS region than to a first side of the second MOS region opposite the boundary.

Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.

Abstract: A semiconductor package includes: a first redistribution structure having a first surface and a second surface opposing the first surface, and including a first insulating layer and a first redistribution layer disposed on the first insulating layer; a semiconductor chip disposed on the first surface of the first redistribution structure, and including a connection pad electrically connected to the first redistribution layer and embedded in the first insulating layer; a vertical connection structure disposed on the first surface and electrically connected to the first redistribution layer; an encapsulant encapsulating at least a portion of each of the semiconductor chip and the vertical connection structure; a second redistribution structure disposed on the encapsulant and including a second redistribution layer electrically connected to the vertical connection structure; and a connection bump disposed on the second surface and electrically connected to the first redistribution layer.

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Abstract: A component carrier with a first component carrier structure including a first stack which has at least one first electrically conductive layer structure and at least one first electrically insulating layer structure is disclosed. The at least one first electrically conductive layer structure has a first contact element which extends up to a first contact surface of the first stack. An electrically conductive connection medium is directly connected to the first contact element at the first contact surface by filling at least one recess of the first contact element. The at least one recess having a larger dimensioned cavity delimited by a smaller dimensioned surface profile.

Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

Abstract: A display panel and a manufacturing method thereof are provided. The display panel includes a substrate, an encapsulation layer, a black matrix layer, and an oleophobic layer. The encapsulation layer is disposed on a surface of the substrate. The black matrix layer is disposed on the encapsulation layer. The black matrix layer includes a through hole. The through hole extends through the black matrix layer to expose the encapsulation layer. The oleophobic layer covers the black matrix layer.

Abstract: A device including a first structure and a second structure is provided.