Patents Examined by Phat X. Cao
  • Patent number: 10319903
    Abstract: Some embodiments include a magnetic tunnel junction device having a first magnetic electrode, a second magnetic electrode, and a tunnel insulator material between the first and second magnetic electrodes. A tungsten-containing material is directly against one of the magnetic electrodes. In some embodiments the tungsten-containing material may be in a first crystalline lattice arrangement, and the directly adjacent magnetic electrode may be in a second crystalline lattice arrangement different from said first crystalline lattice arrangement. In some embodiments the tungsten-containing material, the first magnetic electrode, the tunnel insulator material and the second magnetic electrode all comprise a common crystalline lattice arrangement.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Sumeet C. Pandey
  • Patent number: 10319724
    Abstract: Some embodiments include a memory cell having a first transistor supported by a semiconductor base, and having second and third transistors above the first transistor and vertically stacked one atop the other. Some embodiments include a memory cell having first, second and third transistors. The third transistor is above the second transistor, and the second and third transistors are above the first transistor. The first transistor has first and second source/drain regions, the second transistor has third and fourth source/drain regions, and the third transistor has fifth and sixth source/drain regions. A read bitline is coupled with the sixth source/drain region. A write bitline is coupled with the first source/drain region. A write wordline includes a gate of the first transistor. A read wordline includes a gate of the third transistor. A capacitor is coupled with the second source/drain region and with a gate of the second transistor.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: June 11, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Suraj J. Mathew, Kris K. Brown, Raghunath Singanamalla, Vinay Nair, Fawad Ahmed, Fatma Arzum Simsek-Ege, Diem Thy N. Tran
  • Patent number: 10319714
    Abstract: High voltage drain-extended metal-oxide-semiconductor (DEMOS) bipolar switches for electrical overstress protection are provided. In certain configurations herein, an electrical overstress switch embodiment for providing electrical overstress protection, such as electrostatic discharge/electrical overstress (ESD/EOS) protection includes both a DEMOS device and an embedded bipolar device. The switch is implemented to achieve the advantages provided by the combined conduction of DEMOS and bipolar devices. For example, the DEMOS device provides surface conduction at the gate region for relatively fast switch device turn on and low voltage overshoot, while the bipolar device provides high current conduction during stress condition and a high holding voltage characteristics to prevent latch-up in mission critical integrated circuit applications.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 11, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Sirui Luo, Javier Alejandro Salcedo
  • Patent number: 10297675
    Abstract: Methods of forming a field-effect transistor and structures for a field-effect transistor. A gate structure is formed that overlaps with a channel region in a semiconductor fin. The semiconductor fin is etched with a first etching process to form a first cavity extending into the semiconductor fin adjacent to the channel region. The semiconductor fin is etched with a second etching process to form a second cavity that is volumetrically smaller than the first cavity and that adjoins the first cavity.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 21, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alina Vinslava, Hsien-Ching Lo, Yongjun Shi, Jianwei Peng, Jianghu Yan, Yi Qi
  • Patent number: 10297666
    Abstract: Supposing x is defined as a position of an end of a depletion layer extending when a rated voltage V [V] is applied to a rear surface electrode, W1 is defined as a distance between the position x and an outer peripheral edge of a surface electrode in an outer peripheral direction, W2 is defined as a distance between the position x and an outer peripheral edge of a field insulating film in the outer peripheral direction, t [?m] is defined as a film thickness t [?m] of the field insulating film, a layout of a terminal part is defined so that an electrical field in the field insulating film at the position x expressed as W2V/t(W1+W2) is 3 MV/cm or smaller.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: May 21, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kohei Ebihara, Hiroshi Watanabe
  • Patent number: 10290778
    Abstract: A semiconductor device in which wet-spreading of an adhesive member for bonding the semiconductor element on a base body is suppressed. The semiconductor device includes a base body, and a semiconductor element bonded on the base body via an adhesive member. The adhesive member contains surface-treated particles, or particles that coexist with a dispersing agent. At least a part of the marginal portion of the adhesive member is a region where the particles are unevenly distributed.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: May 14, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Masafumi Kuramoto, Toshifumi Imura, Tomoki Tanisada
  • Patent number: 10287161
    Abstract: An integrated device package is disclosed. The package can include a carrier, such as first integrated device die, and a second integrated device die stacked on the first integrated device die. The package can include a buffer layer which coats at least a portion of an exterior surface of the first integrated device die and which is disposed between the second integrated device die and the first integrated device die. The buffer layer can comprise a pattern to reduce transmission of stresses between the first integrated device die and the second integrated device die.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: May 14, 2019
    Assignee: ANALOG DEVICES, INC.
    Inventors: Xiaojie Xue, Michael J. Zylinski, Thomas M. Goida, Kathleen O. O'Donnell
  • Patent number: 10276552
    Abstract: A semiconductor module, comprises a substrate plate; a semiconductor switch chip and a diode chip attached to a collector conductor on the substrate plate, wherein the diode chip is electrically connected antiparallel to the semiconductor switch chip; wherein the semiconductor switch chip is electrically connected via bond wires to an emitter conductor on the substrate plate providing a first emitter current path, which emitter conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; wherein a gate electrode of the semiconductor switch chip is electrically connected via a bond wire to a gate conductor on the substrate plate providing a gate current path, which gate conductor is arranged oppositely to the semiconductor switch chip with respect to the diode chip; and wherein a protruding area of the emitter conductor runs besides the diode chip towards the first semiconductor switch chip and the first semiconductor switch chip is directly connected via a bond wire with t
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: ABB Schweiz AG
    Inventors: Samuel Hartmann, Ulrich Schlapbach
  • Patent number: 10269900
    Abstract: Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a semiconductor oxide, the semiconductor oxide includes a compound of a semiconductor element and oxygen. A semiconductor film layer is over the adhesion layer, the semiconductor film layer being a material that includes the semiconductor element, the semiconductor film layer having a different composition than the adhesion layer. Bonds at an interface between the insulator layer and the adhesion layer comprise oxygen-hydrogen bonds and oxygen-semiconductor element bonds. An interface between a dummy gate and a gate dielectric layer of a gate-last transistor structure may be similarly formed.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Ming Liao, Chun-Heng Chen, Sheng-Po Wu, Ming-Feng Hsieh, Hongfa Luan
  • Patent number: 10269759
    Abstract: A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a landing trace including a distal end, a conductive pillar extending at least to the distal end of the landing trace; and a solder feature electrically coupling the landing trace and the conductive pillar. In an embodiment, the conductive pillar overhangs the end surface of the landing trace. In another embodiment, the landing trace includes one or more recesses for trapping the solder feature after reflow. Therefore, a wetting area available to the solder feature is increased while permitting the bump pitch of the package to remain small.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Liang Lin, Chen-Shien Chen, Tin-Hao Kuo
  • Patent number: 10262948
    Abstract: A semiconductor module manufacturing method, including preparing an external terminal that is of a pin shape and that has an outflow prevention portion formed on an outer surface portion thereof, attaching the external terminal to a substrate and electrically connecting the external terminal to the substrate, preparing a transfer molding die including a first mold portion and a second mold portion, which are combinable by attaching a parting surface of the first mold portion to a parting surface of the second mold portion, to thereby form a first cavity and a second cavity that are in communication with each other, combining the first and second mold portions to accommodate the substrate and the external terminal respectively in the first and second cavities, and to sandwich the outflow prevention portion between the first and second mold portions, and encapsulating the substrate by injecting resin into the first cavity.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tomomi Nonaka
  • Patent number: 10256335
    Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervene
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 9, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Yamamoto, Tetsuya Fujiwara, Minoru Akutsu, Ken Nakahara, Norikazu Ito
  • Patent number: 10256222
    Abstract: A light emitting diode substrate includes a substrate, a plurality of first light emitting diode and second light emitting diode. The first light emitting diode are disposed on the substrate and arranged along a first direction and a second direction to form a first array. The first light emitting diode have a first side length extending along the first direction and a second side length extending along the second direction. The second light emitting diode are disposed on the substrate and arranged along the first direction and the second direction to form a second array. The second light emitting diode have a third side length extending along the first direction and a forth side length extending along the second direction. A first difference between the first side length and the third side length is less than a second difference between the second side length and the forth side length.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 9, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Tung-Kai Liu, Tsau-Hua Hsieh, Bo-Feng Chen, Wan-Ling Huang
  • Patent number: 10224337
    Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 5, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Luan C. Tran, Hongbin Zhu, John D. Hopkins, Yushi Hu
  • Patent number: 10211184
    Abstract: A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of the first package substrate, a second package substrate having a second plurality of lead fingers, wherein each of the second plurality of lead fingers extends over the first die and the second package substrate is electrically isolated from the first package substrate. The device also includes a second die attached to a first major surface of the second package substrate, over the first die, and an encapsulant surrounding the first die, the first package substrate, the second die, and the second package substrate, wherein the encapsulant exposes a portion of the first package substrate and a portion of the second package substrate.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: February 19, 2019
    Assignee: NXP USA, Inc.
    Inventors: Nishant Lakhera, Navas Khan Oratti Kalandar, Akhilesh K. Singh
  • Patent number: 10205002
    Abstract: The present disclosure generally relate to methods of processing a substrate in an epitaxy chamber. The method includes exposing a substrate having one or more fins to a group IV-containing precursor and a surfactant containing antimony to form an epitaxial film over sidewalls of the one or more fin structures, wherein the surfactant containing antimony is introduced into the epitaxy chamber before epitaxial growth of the epitaxial film, and a molar ratio of the surfactant containing antimony to the group IV-containing precursor is about 0.0001 to about 10.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: February 12, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xinyu Bao, Chun Yan, Errol Antonio C. Sanchez, Hua Chung
  • Patent number: 10192899
    Abstract: A display includes a first substrate, a second substrate, a plurality of pixels and a photo-catalyst layer. The plurality of pixels are disposed between the first substrate and the second substrate. The photo-catalyst layer is disposed above a surface of the second substrate facing the first substrate or above a surface of the first substrate facing the second substrate. Manufacturing methods of a display are additionally disclosed.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 29, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventor: Shih-Hsing Hung
  • Patent number: 10186673
    Abstract: Articles utilizing polymeric dielectric materials for gate dielectrics and insulator materials are provided along with methods for making the articles. The articles are useful in electronics-based devices that utilize organic thin film transistors.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: January 22, 2019
    Assignee: Corning Incorporated
    Inventors: Robert Alan Bellman, Mingqian He, Timothy Edward Myers, Weijun Niu, David Neal Schissel, Kristi Lynn Simonton, Arthur Lawrence Wallace
  • Patent number: 10186568
    Abstract: An organic light emitting display device includes a thin film transistor (TFT) including a gate electrode and a source electrode. An anode electrode is disposed on the TFT, and a cathode electrode disposed on an organic emission layer is connected to an auxiliary electrode which is disposed on a same layer on which the anode electrode is disposed. A signal pad disposed in a pad area of a substrate is disposed on a same layer on which the gate electrode is disposed in an active area of the substrate. A pad electrode disposed on the signal pad is connected to the signal pad through a contact hole.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 22, 2019
    Assignee: LG DISPLAY CO., LTD.
    Inventors: SeJune Kim, Joonsuk Lee, SoJung Lee, Jin-Hee Jang, Jonghyeok Im, JaeSung Lee
  • Patent number: 10181548
    Abstract: A light emitting diode includes: a substrate; a semiconductor stack disposed on the substrate and including a lower semiconductor layer, an upper semiconductor layer and an active layer interposed between the lower semiconductor layer and the upper semiconductor layer, the semiconductor stack having an isolation groove exposing the substrate through the upper semiconductor layer, the active layer and the lower semiconductor layer; a first electrode pad and an upper extension portion electrically connected to the upper semiconductor layer; a second electrode pad and a lower extension portion electrically connected to the lower semiconductor layer; a connecting portion connecting the upper extension portion and the lower extension portion to each other across the isolation groove; a first current blocking layer interposed between the lower extension portion and the lower semiconductor layer; and a second current blocking layer interposed between the second electrode pad and the lower semiconductor layer.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: January 15, 2019
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Keum Ju Lee, Seom Geun Lee, Kyoung Wan Kim, Yong Woo Ryu, Mi Na Jang