Abstract: An electronic package is provided and includes a carrier for carrying electronic components. Electrical contact pads of the carrier for planting solder balls are connected with a plurality of columnar conductors, and the conductors are electrically connected to a circuit portion in the carrier. By connecting a plurality of conductors with a single electrical contact pad, structural stress can be distributed and breakage of the circuit portion can be prevented.

Abstract: A semiconductor device package, along with methods of forming such, are described. The semiconductor device package includes a first semiconductor device structure having a first substrate, two first devices disposed on the first substrate, a first interconnection structure disposed over the first substrate and the two first devices, and a first thermal feature disposed through the first substrate and the first interconnection structure. The semiconductor device package further includes a second semiconductor device structure disposed over the first semiconductor device structure having a second interconnection structure disposed over the first interconnection structure, a second substrate disposed over the second interconnection structure, two second devices disposed between the second substrate and the second interconnection structure, and a second thermal feature disposed through the second substrate and the second interconnection structure.

Abstract: A system substrate package, a system package, and methods of forming the same are described herein. The system substrate package includes an integrated substrate with multiple discrete interconnect structures. In embodiments the multiple discrete interconnect structures are placed and encapsulated and have a gap formed between the multiple discrete interconnect structures. The system substrate package reduces package warpage and mitigates board level reliability issues.

Abstract: The present invention provides a method of forming a metal grid, a backside illuminated (BSI) image sensor, and a method of forming the BSI image sensor. In the methods, an etch stop layer and a metal material layer are successively deposited in geometric conformity over a substrate already formed therein with a recess and a conductive pillar, followed by the formation of a bonding pad on the metal material layer in the recess. After that, a dielectric cap layer is deposited and etched together with the metal material layer and the etch stop layer to form the metal grid. According to the present invention, the deposited metal material layer has reduced surface roughness, which results in improved thickness uniformity of the resulting metal grid. The metal grid is overall easier to form, resulting in savings in cost and increased performance of the device being fabricated.

Abstract: A method of forming stacked vertical field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner. The method further includes forming channels through the layer stack, a liner layer on the sidewalls of the channels, and a vertical pillar in the channels.

Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Abstract: The present disclosure provides a semiconductor device and a fabrication method thereof. The semiconductor device includes a III-nitride layer, a gate, a connection structure, and a gate bus. The gate is disposed over the III-nitride layer. The connection structure is disposed over the gate. The gate bus extends substantially in parallel to the gate and disposed over the connection structure from a top view perspective. The gate bus is electrically connected to the gate through the connection structure.

Abstract: Methods of forming devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. A self-assembled monolayer (SAM) is formed on the bottom of the gap, and a barrier layer is formed on the SAM before selectively depositing a metal liner on the barrier layer. The SAM is removed after selectively depositing the metal liner on the barrier layer.

Abstract: A semiconductor device and method of manufacture is provided including a redistribution structure; a plurality of core substrates attached to the redistribution structure using conductive connectors, each core substrate of the plurality of core substrates comprising a plurality of conductive posts; and one or more molding layers encapsulating the plurality of core substrates, where the one or more molding layers extends along sidewalls of the plurality of core substrates, and where the one or more molding layers extends along a portion of a sidewall of each of the conductive posts.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a first silicon fin having a longest dimension along a first direction. A second silicon fin having a longest dimension is along the first direction. An insulator material is between the first silicon fin and the second silicon fin. A gate line is over the first silicon fin and over the second silicon fin along a second direction, the second direction orthogonal to the first direction, the gate line having a first side and a second side, wherein the gate line has a discontinuity over the insulator material, the discontinuity filled by a dielectric plug.

Abstract: A light emitting diode including a substrate having a first area and a second area defined by an isolation groove line, a semiconductor stack disposed on the substrate and including a lower semiconductor layer, an upper semiconductor layer, an active layer, a first electrode pad electrically connected to the lower semiconductor layer, a second electrode pad electrically connected to the upper semiconductor layer, and a connecting portion electrically connecting the semiconductor stack disposed in the first and second areas to each other, and including a first portion, a second portion, and a third portion extending from a second distal end of the first portion, in which the isolation groove line is disposed between the first and second electrode pads and exposes the substrate, the first portion extends along a first direction substantially parallel to an extending direction of the isolation groove line, and the second and third portions extend in a second direction crossing the first direction.

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, and a heat sink lid. The die is disposed on the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies.

Abstract: Expansion compensating structures are formed in redistribution layers of a wafer-level chip-scale integrated circuit package (WLCSP) or other IC package having a low-expansion substrate. The structures include micromechanical actuators designed and oriented to move solder bumps attached to them in the same direction and distance as a function of temperature as do pads to which they may be connected on a higher-expansion substrate such as a printed circuit board. Expansion compensated IC packages incorporating these expansion compensating structures are provided, as well as expansion compensated assemblies containing one or more of these IC packages. Methods of fabricating expansion compensated IC packages requiring minimal changes to existing commercial WLCSP fabrication processes are also provided. These devices and methods result in assemblies having improved board-level reliability during thermal cycling, and allow the use of larger IC die sizes in WLCSP technology.

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.

Abstract: A method for fabricating a semiconductor component includes forming an interlayer dielectric (ILD) layer on a substrate, forming a trench in the interlayer dielectric layer, forming a metal gate in the trench, removing a portion of the metal gate protruding from the ILD layer, reacting a reducing gas with the metal gate, and removing a top portion of the metal gate.

Abstract: An arrayed switch circuit includes a substrate, signal conductive pads and signal expansion pins. The signal conductive pads are disposed on the substrate at intervals, and the signal conductive pads are arranged to form a signal conductive pad array. Each of the signal conductive pads has a row position and a column position in the signal conductive pad array. A row signal switch is provided between any two adjacent signal conductive pads corresponding to the same row position, and a column signal switch is provided between any two adjacent signal conductive pads corresponding to the same column position. The signal expansion pins are connected to the signal conductive pads located on at least one side of the signal conductive pad array through signal expansion switches respectively.

Abstract: A superstrate can comprise a superstrate blank and a coating overlying an outer surface of the superstrate blank. The superstrate blank can comprises a central region and a tapered edge region, wherein the tapered edge region has an average taper angle of not greater than 20 degrees relative to a length direction of the superstrate blank. In one embodiment, the coating of the superstrate can be applied by spin coating and may have an edge bead below a plane of the coating surface within the central region.

Abstract: A semiconductor package is configured to include a package substrate, a semiconductor chip disposed on the package substrate, and bonding wires. The package substrate includes a first column of bond fingers disposed in a first layer and a second column of bond fingers disposed in a second layer. The semiconductor chip includes a first column of chip pads arrayed in a first column and a second column of chip pads arrayed in a second column adjacent to the first column. The first column of chip pads are connected to the first column of bond fingers, respectively, through first bonding wires, and the second column of chip pads are connected to the second column of bond fingers, respectively, through second bonding wires.

Abstract: An integrated circuit including: a power rail including first and second conductive lines spaced apart from each other in a vertical direction, wherein the first and second conductive lines extend in parallel to each other in a first horizontal direction, and are electrically connected to each other, to supply power to a first standard cell, wherein the first and second conductive lines are disposed at a boundary of the first standard cell; and a third conductive line between the first and second conductive lines and extending in a second horizontal direction orthogonal to the first horizontal direction, to transfer an input signal or an output signal of the first standard cell.