Abstract: A semiconductor package includes a plurality of stack modules which are vertically stacked. Each of the stack modules includes an interposing bridge, a semiconductor dies, and redistribution lines. The stack modules are provided by rotating each of the stack modules by different rotation angles corresponding to multiples of a reference angle and by vertically stacking the rotated stack modules. The interposing bridge includes a plurality of sets of through vias, and each set of through vias includes through vias arrayed in a plurality of columns. The plurality of sets of through vias are disposed in respective ones of divided regions of the interposing bridge. If the plurality of sets of through vias are rotated by the reference angle, then the rotated through vias overlap with the plurality of sets of through vias which are originally located. The redistribution lines connect the semiconductor dies to the plurality of sets of through vias.

Abstract: The present disclosure relates to a driving backplane, a micro-LED display panel and a micro-LED display device. The driving backplane, includes a plurality of pixel units arranged in an array, each of the pixel units comprising: an anode lead; a cathode lead at a side of the anode lead; and at least two pairs of electrodes, each pair of electrodes of the at least two pairs of electrodes including an anode and a cathode oppositely disposed, the anode being electrically connected to the anode lead, and the cathode being electrically connected to the cathode lead. In the course of using the foregoing driving backplane of the micro-LED display panel, it is only necessary to solder an LED chip on one pair of electrodes of the at least two pairs of electrodes.

Abstract: A manufacturing method of a light emitting diode apparatus is provided. This method includes forming a light emitting diode on the substrate, forming a light leakage preventing layer to surround the side surface of the light emitting diode, etching a region corresponding to the light emitting diode in the substrate, and bonding a wavelength converting material to a lower portion of the light emitting diode in the etched region, in which the wavelength converting material includes a semiconductor layer including a quantum well layer.

Abstract: A semiconductor device includes a landing pad, a first insulating pattern in contact with a lower portion of a side surface of the landing pad, a pad oxide layer having a lateral portion disposed on a portion of an upper surface of the landing pad and a vertical portion in contact with an upper portion of the side surface of the landing pad, a second insulating pattern in contact with an upper surface of the first insulating pattern and covering the first insulating pattern and the pad oxide layer, and a lower electrode that vertically passes through the second insulating pattern and is in contact with a portion of the upper surface and an upper portion of a side surface of the landing pad.

Abstract: A transistor structure of a semiconductor memory device comprises: an active area having a plurality of trenches and a substrate surface, the trenches having openings oriented toward the substrate surface; a plurality of gate structures embedded in the trenches, wherein the substrate surface comprises source regions located on outer sides of the gate structures and a drain region located between the gate structures; node contacts each disposed on one of the source regions; a bit line contact disposed on the drain region and connectable to a bit line, the node contacts sharing the bit line contact through adjacent gate structures, wherein the drain region comprises a first ion implantation layer extending inwardly from the bit line contact, each of the source regions comprising a second ion implantation layer extending inwardly from a corresponding node contact, the first ion implantation layer being deeper than the second ion implantation layer.

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Abstract: A method for fabricating semiconductor die with die-attach preforms is disclosed. In embodiments, the method includes: applying an uncured die-attach paste material to a surface of a forming substrate to form one or more die-attach preforms, the surface of the forming substrate formed from a hydrophobic material; curing the one or more die-attach preforms; performing one or more planarization processes on the one or more die-attach preforms; coupling a first surface of a semiconductor die to a handling tool; and bonding a second surface of the semiconductor die to at least one die-attach preform of the one or more die-attach preforms.

Abstract: A display device is provided. The display device includes a substrate, and a first sub-pixel and a second sub-pixel disposed on the substrate, wherein the first sub-pixel and the second sub-pixel respectively correspond to two different colors. The first sub-pixel includes a first light-emitting element and a first wavelength conversion layer adjacent to the first light-emitting element, wherein a light emitted from the first light-emitting element passes through the first wavelength conversion layer. The second sub-pixel includes a second light-emitting element and a second wavelength conversion layer adjacent to the second light-emitting element, wherein a light emitted from the second light-emitting element passes through the second wavelength conversion layer. An area of the first wavelength conversion layer and an area of the second wavelength conversion layer are different.

Abstract: A semiconductor structure having a Si substrate heterointegrated with GaN and a method for fabricating the same is disclosed. The method uses a (100) silicon substrate to fabricate a hundred nanometer scale hole and uses wet etching to etch the silicon substrate, thereby exposing the (111) crystal surface of the silicon substrate. The (111) crystal surface is used as a nucleating crystal surface of an AlN buffer layer and GaN. When GaN is grown, silane is reacted with GaN to adjust the concentration of doping silicon atoms into GaN, thereby forming a semiconductor structure having a Si substrate heterointegrated with GaN.

Abstract: A method used in forming a memory array comprises forming a substrate comprising a conductor tier comprising an upper conductor material and a lower conductor material, and a stack comprising vertically-alternating first tiers and second tiers above the conductor tier. Horizontally-elongated trenches are formed through the stack to the upper conductor material and the lower conductor material. At least one of the upper and lower conductor materials have an exposed catalytic surface in the trenches. Metal material is electrolessly deposited onto the catalytic surface to cover the upper conductor material and the lower conductor material within the trenches. Channel-material strings of memory cells are formed and extend through the second tiers and the first tiers. Other embodiments, including structure independent of method, are disclosed.

Abstract: A power delivery device includes a printed circuit board (PCB), a package device, and a chip connecting device. The PCB is configured to receive a first reference voltage and a second reference voltage. The package device is coupled to the PCB, and includes a bump array. The chip connecting device is coupled to the bump array of the package device, and configured to output a first supply voltage and a second supply voltage. The bump array includes first bumps and second bumps. The first bumps are configured to transmit the first reference voltage. The second bumps are configured to transmit the second reference voltage. The first bumps and the second bumps are disposed in parallel.

Abstract: A semiconductor package includes: a connection structure including one or more redistribution layers; a core structure disposed on a surface of the connection structure; a semiconductor chip disposed on the surface and including connection pads electrically connected to the redistribution layers of the connection structure; a first encapsulant disposed on the surface and covering at least a portion of each of the core structure and the semiconductor chip; an antenna substrate disposed on the first encapsulant and including one or more wiring layers, at least a portion of the wiring layers including an antenna pattern; and a through via penetrating at least a portion of each of the connection structure, the core structure, the first encapsulant, and the antenna substrate.

Abstract: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.

Abstract: The present disclosure includes memory having a continuous channel, and methods of processing the same. A number of embodiments include forming a vertical stack having memory cells connected in series between a source select gate and a drain select gate, wherein forming the vertical stack includes forming a continuous channel for the source select gate, the memory cells, and the drain select gate, and removing a portion of the continuous channel for the drain select gate such that the continuous channel is thinner for the drain select gate than for the memory cells and the source select gate.

Abstract: An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer. The nucleation layer is disposed on the substrate, and the nucleation layer consists of a plurality of regions in a thickness direction, wherein a chemical composition of the region is Al(1?x)InxN, where 0?x?1. The buffer layer is disposed on the nucleation layer, and a thickness of the nucleation layer is less than a thickness of the buffer layer. The nitride layer is disposed on the buffer layer, wherein a roughness of a surface of the nucleation layer in contact with the buffer layer is greater than a roughness of a surface of the buffer layer in contact with the nitride layer.

Abstract: An electroluminescent display device includes: a substrate including: a first subpixel, a second subpixel, and a third subpixel, an insulating layer on the substrate, the insulating layer including a trench, a first electrode in each of the first to third subpixels on the insulating layer, an emission layer on the first electrode and the insulating layer, and a second electrode on the emission layer, wherein the trench is in a boundary between the first subpixel and the second subpixel, and wherein the trench is not in a boundary between the second subpixel and the third subpixel.

Abstract: A semiconductor device including a substrate including an active pattern; a gate electrode crossing the active pattern; a source/drain pattern adjacent to one side of the gate electrode and on an upper portion of the active pattern; an active contact electrically connected to the source/drain pattern; and a silicide layer between the source/drain pattern and the active contact, the source/drain pattern including a body part including a plurality of semiconductor patterns; and a capping pattern on the body part, the body part has a first facet, a second facet on the first facet, and a corner edge defined where the first facet meets the second facet, the corner edge extending parallel to the substrate, the capping pattern covers the second facet of the body part and exposes the corner edge, and the silicide layer covers a top surface of the body part and a top surface of the capping pattern.

Abstract: A structure includes a die substrate; a passivation layer on the die substrate; first and second interconnect structures on the passivation layer; and a barrier on the passivation layer, at least one of the first or second interconnect structures, or a combination thereof. The first and second interconnect structures comprise first and second via portions through the passivation layer to first and second conductive features of the die substrate, respectively. The first and second interconnect structures further comprise first and second pads, respectively, and first and second transition elements on a surface of the passivation layer between the first and second via portion and the first and second pad, respectively. The barrier is disposed between the first pad and the second pad. The barrier does not fully encircle at least one of the first pad or the second pad.

Abstract: A semiconductor device may include active pattern, a silicon liner, an insulation layer, an isolation pattern and a transistor. The active pattern may protrude from a substrate. The silicon liner having a crystalline structure may be formed conformally on surfaces of the active pattern and the substrate. The insulation layer may be formed on the silicon liner. The isolation pattern may be formed on the insulation layer to fill a trench adjacent to the active pattern. The transistor may include a gate structure and impurity regions. The gate structure may be disposed on the silicon liner, and the impurity regions may be formed at the silicon liner and the active pattern adjacent to both sides of the gate structure.

Abstract: A multi-layer substrate includes: a first insulating layer; a conductor layer that is provided on an upper surface of the first insulating layer and that has a penetrating portion; a second insulating layer that covers the conductor layer and that is stacked on the upper surface of the first insulating layer; a via hole that penetrates the second insulating layer from an upper surface of the second insulating layer to reach an inside of the first insulating layer and that includes the penetrating portion; and an insulating member with which the via hole is filled. The conductor layer has a portion exposed in the via hole, and the insulating member covers an upper surface and a lower surface of the conductor layer exposed in the via hole through the penetrating portion of the conductor layer.