Abstract: LED packages are disclosed capable of emitting a range of colors including white light, while still emitting that can have a high color rendering index (CRI). The LED packages can have a simplified reflective cup arrangement and improved lead frame design. The LED packages according to the present invention comprise one or more LED WITH PHOSPHORs for high CRI lighting applications, along with multiple narrowband emitters (e.g. RGB LEDs), but do not have a dam or partition to segregate the LED WITH PHOSPHOR from the multiple emitters. This results in a LED package that is less complex and easier to manufacture, while still providing the desired flexibility in LED package emissions.

Abstract: A terminal structure includes a wiring layer, a protective insulation layer, an open portion, and a connection terminal. The protective insulation layer covers the wiring layer. The open portion extends through the protective insulation layer in a thickness-wise direction to expose part of an upper surface of the wiring layer. The connection terminal is formed on the wiring layer exposed from the open portion. The open portion includes a wall surface, a depression, and a projection. The wall surface extends downward from an upper surface of the protective insulation layer. The depression is depressed into the protective insulation layer from the wall surface toward an outer side of the open portion. The projection is formed under the depression, continuously with the depression, and projected from the depression into the open portion further inward than the wall surface in a plan view. The depression is filled with the connection terminal.

Abstract: An epitaxial structure includes a substrate, a nucleation layer, a buffer layer, and a nitride layer orderly. The nucleation layer consists of regions in a thickness direction, wherein a chemical composition of the regions is Al(1?x)InxN, where 0?x?1. The x value consists of four sections of variation along the thickness direction, in which a first fixed region has a maximum value, a first gradient region gradually changes from the maximum value to a minimum value, a second fixed region has the minimum value, and a second gradient region gradually changes from the minimum value to the maximum value. An absolute value of a gradient slope of the first and second gradient regions is 0.1%/nm to 50%/nm. A surface roughness of the nucleation layer in contact with the buffer layer is greater than that of the buffer layer in contact with the nitride layer.

Abstract: A target and method for using the same in the measurement of misregistration between at least a first layer and a second layer formed on a wafer in the manufacture of functional semiconductor devices on the wafer, the functional semiconductor devices including functional device structures (FDSTs), the target including a plurality of measurement structures (MSTs), the plurality of MSTs being part of the first layer and the second layer and a plurality of device-like structures (DLSTs), the plurality of DLSTs being part of at least one of the first layer and the second layer, the DLSTs sharing at least one characteristic with the FDSTs and the MSTs not sharing the at least one characteristic with the FDSTs.

Abstract: A semiconductor package including a semiconductor die, an encapsulant, an electrical connector, a conductive pad and an inter-dielectric layer is provided. The encapsulant encapsulates the semiconductor die. The electrical connector is disposed over the semiconductor die. The conductive pad contacts the electrical connector and is disposed between the semiconductor die and the electrical connector. The inter-dielectric layer is disposed over the semiconductor die, wherein the inter-dielectric layer comprises an opening, and a portion of the opening is occupied by the conductive pad and the electrical connector.

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.

Abstract: Some embodiments include a memory cell having a conductive gate, and having a charge-blocking region adjacent the conductive gate. The charge-blocking region includes silicon oxynitride and silicon dioxide. A charge-storage region is adjacent the charge-blocking region. Tunneling material is adjacent the charge-storage region. Channel material is adjacent the tunneling material. The tunneling material is between the channel material and the charge-storage region. Some embodiments include memory arrays. Some embodiments include methods of forming assemblies (e.g., memory arrays).

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

Abstract: A memory device includes a first semiconductor wafer portion including two or more adjacent quasi-volatile memory circuits formed on a common semiconductor substrate where each quasi-volatile memory circuit being isolated from an adjacent quasi-volatile memory circuit by scribe lines; and a second semiconductor wafer portion including at least one memory controller circuit formed on a semiconductor substrate. The memory controller circuit includes logic circuits and interface circuits. The memory controller circuit is interconnected to the two or more adjacent quasi-volatile memory circuits of the first semiconductor wafer portion through interconnect structures and the memory controller circuit operates the two or more quasi-volatile memory circuits as one or more quasi-volatile memories.

Abstract: An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.

Abstract: A semiconductor device is provided.

Abstract: Systems for apparatuses formed of light emitting devices. Solutions for controlling the off-state appearance of lighting system designs is disclosed. Thermochromic materials are selected in accordance with a desired off-state of an LED device. The thermochromic materials are applied to a structure that is in a light path of light emitted by the LED device. In the off-state the LED device produces a desired off-state colored appearance. When the LED device is in the on-state, the thermochromic materials heat up and become more and more transparent. The light emitted from the device in its on-state does not suffer from color shifting due to the presence of the thermochromic materials. Furthermore, light emitted from the LED device in its on-state does not suffer from attenuation due to the presence of the thermochromic materials. Techniques to select and position thermochromic materials in or around LED apparatuses are presented.

Abstract: A display device including: a substrate including a display area, a peripheral area, and a pad area; a first main voltage line in the peripheral area, and a first connector extending from the first main voltage line to the pad area; and a second main voltage line in the peripheral area, and a second connector extending from the second main voltage line to the pad area, wherein each of the first connector and the second connector includes a first and second layer overlapping each other with a first insulating layer therebetween, the first insulating layer is in the display area and the peripheral area, the peripheral area includes an open area exposing the first and second connector and surrounding the display area, and the first insulating layer includes slits between the first and second connector and extending from an end of the first insulating layer toward the display area.

Abstract: A semiconductor device assembly and associated methods are disclosed herein. The semiconductor device assembly includes (1) a substrate having a first side and a second side opposite the first side; (2) a first set of stacked semiconductor devices at the first side of the substrate; (3) a second set of stacked semiconductor devices adjacent to one side of the first set of stacked semiconductor devices; (4) a third set of stacked semiconductor devices adjacent to an opposite side of the first set of stacked semiconductor devices; and (5) a temperature adjusting component at the second side and aligned with the second set of stacked semiconductor devices. The temperature adjusting component is positioned to absorb the thermal energy and thereby thermally isolate the second set of stacked semiconductor devices from the first set of stacked semiconductor devices.

Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.

Abstract: The present application provides an electronic package having an optoelectronic component and a laser component disposed on a packaging unit, with the optoelectronic component and the laser component being separated from each other. Since the laser component and the optoelectronic component are separated from each other, the electronic package has a reduced fabrication difficulty and a high yield rate. A method for fabricating the electronic package and an electronic packaging module having the electronic package are also provided.

Abstract: A light emitting device including at least one first light emitting unit including an ultraviolet or violet light emitting diode chip and a first wavelength converter, at least one second light emitting unit including an ultraviolet or violet light emitting diode chip and a second wavelength converter, and at least one third light emitting unit including an ultraviolet or violet light emitting diode chip and a third wavelength converter, in which color coordinates of the first light emitting unit, the second light emitting unit, and the third light emitting unit define a triangular region in a CIE-1931 coordinate system, the triangular region including at least a portion of the Plankian locus, and a maximum color temperature of the Plankian locus included in the triangular region is 5000K or higher, and a minimum color temperature of the Plankian locus included in the triangular region is 3000K or lower.

Abstract: A packaging glass substrate for semiconductor includes a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias penetrating through the glass substrate in a thickness direction, wherein a plain line is a line linking places where the core vias are not formed, a via line is a line linking places where the core vias are formed, a stress difference value (P) is a value according to Equation (1), and the stress difference value (P) is 1.5 MPa or less, Equation (1): P=Vp?Np where P is a stress difference value measured at the same glass substrate, Vp is a difference between the maximum value and the minimum value of stress measured at the via line, and Np is a difference between the maximum value and the minimum value of stress measured at the plain line.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor including a first photodetector and a second photodetector each disposed within a semiconductor substrate. An isolation structure extends from a front-side surface of the semiconductor substrate to a back-side surface of the semiconductor substrate. The front-side surface is opposite the back-side surface and the isolation structure is laterally between the first and second photodetectors. A readout transistor is disposed on the front-side surface of the semiconductor substrate. A first side of the readout transistor overlies the first photodetector and a second side of the readout transistor overlies the second photodetector. The first side is opposite the second side and the readout transistor continuously extends over the isolation structure.

Abstract: Display devices are disclosed herein. In one embodiment, the display device includes a plastic substrate comprising a display area and a non-display area, and a data pad portion disposed on one side of the non-display area, with a flexible circuit board bonded thereto, the display area including a plurality of subpixels positioned on the display area, each subpixel including an organic light-emitting diode that includes an organic layer, wherein the organic layer extends continuously from one side of the display area to the other side of the display area and is arranged in a plurality of lines that are spaced apart from one another and disposed parallel to the data pad portion.