Patents Examined by Phuc T. Dang
  • Patent number: 10910327
    Abstract: A package for an electronic device may include a first layer. The first layer may include a first dielectric material. The first layer may have a planar first surface. The first layer may have a variable thickness. A second layer may be coupled to the first layer. The second layer may include a second dielectric material and may have a planar second surface. The second layer may have a variable thickness. A seam may be located at an interface between the first layer and the second layer, and the seam may have an undulating profile. The package may include at least one electrical trace, for example located in the first layer or the second layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: February 2, 2021
    Assignee: Intel Corporation
    Inventors: Yonggang Li, Brandon C Marin, Vahidreza Parichehreh, Jeremy D Ecton
  • Patent number: 10910291
    Abstract: A method of creating thermal boundaries in a substrate is provided. The method includes forming the substrate with first and second sections to be in direct thermal communication with first and second thermal elements, respectively, machining, in the substrate, first and second cavities for defining a third section of the substrate between the first and second sections and disposing a material having a characteristic thermal conductivity that is substantially less than that of the ceramic in the first and second cavities.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: February 2, 2021
    Assignee: RAYTHEON COMPANY
    Inventor: Thomas P. Sprafke
  • Patent number: 10910366
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) for implementing an artificial neural network (ANN) having a memory die having an array of memory partitions. Each partition of the array of memory partitions is configured to store parameters of a set of neurons. The 3D SIC also has a processing logic die having an array of processing logic partitions. Each partition of the array of processing logic partitions is configured to: receive input data, and process the input data according to the set of neurons to generate output data.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: February 2, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer
  • Patent number: 10903294
    Abstract: A display device includes a display part including a plurality of pixels arranged on a substrate, a plurality of dams in a first peripheral part adjacent to the display part, the plurality of dams being extended in a longitudinal direction of the first peripheral part and arranged in a direction crossing the longitudinal direction, the plurality of dams including a stack of a first organic insulating layer and a second organic insulating layer, and a blocking part disposed between the plurality of dams and corresponding to a removed portion of the first and second organic insulating layers.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki Ho Bang, Nayun Kwak, Eunhye Kim, Sae bom Ahn, Seong Ryoung Lee, Sanghyun Jun, Wonsuk Choi
  • Patent number: 10903073
    Abstract: A method of manufacturing a semiconductor device includes forming a first epitaxial layer on a first substrate. The first substrate includes a first semiconductor material having a first lattice constant and the first epitaxial layer includes a second semiconductor material having a second lattice constant different from the first lattice constant. The method also includes disposing a graphene layer on the first epitaxial layer and forming a second epitaxial layer comprising the second semiconductor material on the graphene layer. This method can increase the substrate reusability, increase the release rate of functional layers, and realize precise control of release thickness.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 26, 2021
    Assignee: Massachusetts Institute of Technology
    Inventors: Jeehwan Kim, Kyusang Lee
  • Patent number: 10903281
    Abstract: Discussed are embodiments of an organic light emitting display device, which includes a plurality of pixels, each including at least one red sub pixel, a plurality of green sub pixels, and at least one blue sub pixel, wherein red sub pixels and blue sub pixels of adjacent pixels are aligned in a first direction and a second direction, wherein green sub pixels of the adjacent pixels are aligned in the first direction and are also aligned in the second direction, wherein the plurality of green sub pixels is disposed between the at least one red sub pixel and the at least one blue sub pixel of each pixel, and wherein the plurality of green sub pixels is offset from the at least one red sub pixel and the at least one blue sub pixel in the first direction and the second direction in the each pixel.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: January 26, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: EuiHyun Chung, Yongmin Jeong
  • Patent number: 10903219
    Abstract: Flash memory technology is disclosed. In one example, a flash memory cell can include a charge storage structure, a control gate laterally separated from the charge storage structure, and at least four dielectric layers disposed between the control gate and the charge storage structure. Associated systems and methods are also disclosed.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Haitao Liu, Guangyu Huang, Krishna K. Parat, Shrotri B. Kunal, Srikant Jayanti
  • Patent number: 10903349
    Abstract: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 26, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Louis Hutin, Sylvain Barraud, Benoit Bertrand, Maud Vinet
  • Patent number: 10903301
    Abstract: A display device includes: a substrate; pixels, the pixels each including at least one transistor and a light emitting device connected to the transistor; data lines and scan lines connected to the pixels; and a power line supplying power to the light emitting device. The transistor includes an active pattern on the substrate, source and drain electrodes each connected to the active pattern, a gate electrode on the active pattern, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer including a first interlayer insulating layer, a second interlayer insulating layer, and a third interlayer insulating layer, which are sequentially stacked, and a protective layer provided on the interlayer insulating layer. The third interlayer insulating layer includes a concave part in a region in which the light emitting device and the second conductive layer overlap with each other, and the second conductive layer is in the concave part.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: January 26, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yang Wan Kim, Hyung Jun Park, Jae Yong Lee, Byung Sun Kim, Su Jin Lee
  • Patent number: 10903348
    Abstract: A semiconductor device includes a semiconductor body including first to fourth semiconductor layers. The second semiconductor layer of second conductivity type is provided on the first semiconductor layer of first conductivity type; the third semiconductor layer of first conductivity type is provided selectively on the second semiconductor layer; and the fourth semiconductor layer of second conductivity type is provided selectively on the second semiconductor layer. The semiconductor device further includes first and second control electrodes. The first and second control electrodes are provided inside the semiconductor body and oppose the second semiconductor layer with first and second insulating films interposed, respectively, and are arranged alternately with a third insulating layer interposed. The first control electrode contacts the third insulating layer at a first surface thereof, and the second control electrode contacts the third insulating layer at a second surface opposite to the first surface.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: January 26, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Matsudai, Yoko Iwakaji, Takeshi Suwa
  • Patent number: 10903298
    Abstract: A display device includes: a plurality of pixels each including a driving thin film transistor and a storage capacitor, wherein each of the pixels further includes: a driving semiconductor layer including a driving channel region, a driving source region, and a driving drain region; a first electrode layer, a portion of the first electrode layer overlapping the driving channel region; a second electrode layer overlapping the first electrode layer; a node connection line having a first side connected to the first electrode layer: a pixel electrode overlapping the first electrode layer and the second electrode layer; and a shielding layer between the first electrode layer and the pixel electrode and overlapping the first electrode layer, the node connection line, and the pixel electrode.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: January 26, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Seungkyu Lee, Taehoon Kwon, Byungsun Kim
  • Patent number: 10892238
    Abstract: A circuit structure including a first signal line and a second signal line is provided. The first signal line includes a first line segment, a first ball grid array pad, and a first through hole disposed between the first line segment and the first ball grid array pad. The second signal line includes a second line segment, a second ball grid array pad, and a second through hole disposed between the second line segment and the second ball grid array pad. In a plan view, a line connecting the center of the first ball grid array pad and the center of the second ball grid array pad has a first distance, a line connecting the center of the first through hole and the center of the second through hole has a second distance, and the first distance is less than the second distance. A chip package is also provided.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: January 12, 2021
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Hung Lin, Sheng-Fan Yang, Yu-Cheng Sun
  • Patent number: 10892181
    Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu, Reinaldo Vega
  • Patent number: 10892442
    Abstract: An organic light emitting diode device can have an enhanced thin film encapsulation layer for preventing moisture from permeating from the outside. The thin film encapsulation layer can have a multilayered structure in which one or more inorganic layers and one or more organic layers are alternately laminated. A barrier can be formed outside of a portion of the substrate on which the organic light emitting diode is formed. The organic layers of the thin film encapsulation layer can be formed inside an area defined by the barrier.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: January 12, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Nam-Jin Kim, Chul-Hwan Park
  • Patent number: 10886411
    Abstract: A semiconductor device includes a substrate, a transistor, a storage capacitor, a first insulating layer, and a second insulating layer. The transistor includes a semiconductor film, a gate insulating film, a first gate electrode, and a second gate electrode. The semiconductor film, the gate insulating film, and the first gate electrode are provided in this order from the substrate. The second gate electrode faces the first gate electrode across the semiconductor film. The storage capacitor includes a lower electrode and an upper electrode that are provided in this order from the substrate. The upper electrode faces the lower electrode and includes the same material as the semiconductor film. The first insulating layer is provided between the second gate electrode and the semiconductor film. The second insulating layer is provided between the lower electrode and the upper electrode and has a smaller thickness than the first insulating layer.
    Type: Grant
    Filed: October 30, 2018
    Date of Patent: January 5, 2021
    Assignee: JOLED INC.
    Inventor: Yasuhiro Terai
  • Patent number: 10886197
    Abstract: An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.
    Type: Grant
    Filed: February 23, 2020
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Muthumanickam Sankarapandian, Yongan Xu
  • Patent number: 10886437
    Abstract: An inorganic coating may be applied to bond optically scattering particles or components. Optically scattering particles bonded via the inorganic coating may form a three dimensional film which can receive a light emission, convert, and emit the light emission with one or more changed properties. The inorganic coating may be deposited using a low-pressure deposition technique such as an atomic layer deposition (ALD) technique. Two or more components, such as an LED and a ceramic phosphor layer may be bonded together by depositing an inorganic coating using the ALD technique.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: January 5, 2021
    Assignee: Lumileds LLC
    Inventors: Michael Camras, Jyoti Bhardwaj, Peter J. Schmidt, Niels Jeroen Van Der Veen
  • Patent number: 10879152
    Abstract: An apparatus is provided which comprises: a substrate; a stacked ring structure disposed on the substrate, the stacked ring structure comprising a first ring and a second ring; a first partial through-mold-via (TMV) formed on the first ring; and a second partial TMV formed on the second ring, wherein the first ring and the second ring are stacked such that the first partial TMV is aligned on top of the second partial TMV.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Yi Elyn Xu, Bilal Khalaf
  • Patent number: 10879287
    Abstract: The present technology relates to a solid-state imaging device capable of inhibiting peeling of a fixed charge film while inhibiting dark current, a method of manufacturing the same, and an electronic device. A solid-state imaging device provided with a semiconductor substrate in which a plurality of photodiodes is formed, a groove portion formed in a depth direction from a light incident side for forming an element separating unit between adjacent photoelectric conversion elements on the semiconductor substrate, a first fixed charge film formed so as to cover a surface of a planar portion on the light incident side of the semiconductor substrate, and a second fixed charge film formed so as to cover an inner wall surface of the groove portion formed on the semiconductor substrate is provided. The present technology is applicable to a backside illumination CMOS image sensor, for example.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 29, 2020
    Assignee: SONY CORPORATION
    Inventor: Tadayuki Dofuku
  • Patent number: 10879221
    Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Chih-Hua Chen, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin