Patents Examined by Phuc T. Dang
  • Patent number: 10886197
    Abstract: An Nblock layer is deposited onto a semiconductor substrate that includes metal deposits. A titanium nitride (TiN) layer is deposited directly onto the Nblock layer; an oxide layer is deposited directly onto the TiN layer; and a via hole is formed through the oxide and TiN layer to contact bottom interconnect. The via hole is aligned to one of the metal deposits in the substrate.
    Type: Grant
    Filed: February 23, 2020
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Yann Mignot, Muthumanickam Sankarapandian, Yongan Xu
  • Patent number: 10886437
    Abstract: An inorganic coating may be applied to bond optically scattering particles or components. Optically scattering particles bonded via the inorganic coating may form a three dimensional film which can receive a light emission, convert, and emit the light emission with one or more changed properties. The inorganic coating may be deposited using a low-pressure deposition technique such as an atomic layer deposition (ALD) technique. Two or more components, such as an LED and a ceramic phosphor layer may be bonded together by depositing an inorganic coating using the ALD technique.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: January 5, 2021
    Assignee: Lumileds LLC
    Inventors: Michael Camras, Jyoti Bhardwaj, Peter J. Schmidt, Niels Jeroen Van Der Veen
  • Patent number: 10879273
    Abstract: An active matrix substrate includes a thin film transistor having a gate electrode, an oxide semiconductor layer disposed on the gate electrode via a gate insulating layer, and a source electrode and a drain electrode disposed on the oxide semiconductor layer. A plurality of gate bus lines and the gate electrode are made of a first electrically conductive film. At least part of each of the plurality of source bus lines, the source electrode, and the drain electrode have a multilayer structure including a lower layer that is made of a second electrically conductive film and an upper layer that is made of a first transparent electrically conductive film. Between the plurality of source bus lines and the gate insulating layer, a plurality of first oxide strips extending along the first direction are disposed, the first oxide strips being made of the same oxide semiconductor film as the oxide semiconductor layer.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 29, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hidenobu Kimoto
  • Patent number: 10879184
    Abstract: In one aspect of this disclosure, an electronic device mounting board includes a substrate having a first surface and a second surface opposite to the first surface. The substrate has a first recess located on the first surface and a second recess located on the second surface. The substrate includes an electrode pad. The electrode pad is located in the first recess. The second recess in the substrate contains a reinforcement dividing the second recess into a plurality of recesses. The reinforcement is located separate from the electrode pad or is located to overlap the electrode pad in a plan view.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: December 29, 2020
    Assignee: Kyocera Corporation
    Inventors: Fumiaki Takeshita, Teruaki Nonoyama
  • Patent number: 10879387
    Abstract: Described examples include integrated circuits, drain extended transistors and fabrication methods therefor, including a multi-fingered transistor structure formed in an active region of a semiconductor substrate, in which a transistor drain finger is centered in a multi-finger transistor structure, a transistor body region laterally surrounds the transistor, an outer drift region laterally surrounds an active region of the semiconductor substrate, and one or more inactive or dummy structures are formed at lateral ends of the transistor finger structures.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: December 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, James Robert Todd, Binghua Hu, Xiaoju Wu, Stephanie L. Hilbun
  • Patent number: 10879152
    Abstract: An apparatus is provided which comprises: a substrate; a stacked ring structure disposed on the substrate, the stacked ring structure comprising a first ring and a second ring; a first partial through-mold-via (TMV) formed on the first ring; and a second partial TMV formed on the second ring, wherein the first ring and the second ring are stacked such that the first partial TMV is aligned on top of the second partial TMV.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Yi Elyn Xu, Bilal Khalaf
  • Patent number: 10879287
    Abstract: The present technology relates to a solid-state imaging device capable of inhibiting peeling of a fixed charge film while inhibiting dark current, a method of manufacturing the same, and an electronic device. A solid-state imaging device provided with a semiconductor substrate in which a plurality of photodiodes is formed, a groove portion formed in a depth direction from a light incident side for forming an element separating unit between adjacent photoelectric conversion elements on the semiconductor substrate, a first fixed charge film formed so as to cover a surface of a planar portion on the light incident side of the semiconductor substrate, and a second fixed charge film formed so as to cover an inner wall surface of the groove portion formed on the semiconductor substrate is provided. The present technology is applicable to a backside illumination CMOS image sensor, for example.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: December 29, 2020
    Assignee: SONY CORPORATION
    Inventor: Tadayuki Dofuku
  • Patent number: 10879221
    Abstract: A package-on-package structure includes a first package, a second package and first intermetallic features. The first package includes at least one semiconductor die, an insulating encapsulant, a redistribution layer and conductive pads. The insulating encapsulant is encapsulating the semiconductor die. The redistribution layer is disposed on the insulating encapsulant. The conductive pads are located at a surface of the insulating encapsulant. The second package is stacked on the first package and electrically connected to the conductive pads through connectors. The first intermetallic features are sandwiched in between the conductive pads and the connectors and have a control region and a growth region. The connectors are connected to the control region, and the growth region spreads out from a periphery of the control region such that the spreading of the growth region extends away from the conductive pads in a direction towards the semiconductor die.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Ti Lu, Chih-Hua Chen, Hao-Yi Tsai, Ming-Hung Tseng, Yen-Liang Lin
  • Patent number: 10872974
    Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer having first and second planes; first and second trenches extending in a first direction; first and second gate electrodes; a first silicon carbide region of a first conductivity type; a plurality of second silicon carbide regions of a second conductivity type between the first silicon carbide region and the first plane, located between the first trench and the second trench, and separated from each other in the first direction; a fourth silicon carbide region of the second conductivity type between two of the second silicon carbide regions and contacting the second silicon carbide region; a fifth silicon carbide region of the second conductivity type between the two second silicon carbide regions and contacting the second silicon carbide region; a first electrode contacting the first silicon carbide region; and a second electrode.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: December 22, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Makoto Mizukami, Takuma Suzuki, Yujiro Hara
  • Patent number: 10868187
    Abstract: In some embodiments, in a method, a body structure with a gate structure configured thereon is provided. The gate structure comprises a gate side wall traversing the body structure. A spacer is formed over the gate side wall. A first recess is formed in the body structure. The first recess is formed beside the spacer and extending laterally under the spacer. A recess extension is formed under the first recess to extend a vertical depth of the first recess. Stressor material with a lattice constant different from that of the body structure is grown such that the extended first recess is filled.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: December 15, 2020
    Inventors: Che-Cheng Chang, Chang-Yin Chen, Yung Jung Chang
  • Patent number: 10868090
    Abstract: A display substrate, a manufacture method of a display substrate, and a display panel is provided. The display substrate includes a display region, and a non-display region extending from at least one edge of the display region, wherein the display region includes a display pixel definition layer, the non-display region includes a non-display pixel definition layer, and an adhesive property of the display pixel definition layer to a first pixel material layer in the display pixel definition layer is higher than that of the non-display pixel definition layer to a second pixel material layer in the non-display pixel definition layer.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: December 15, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wenjun Hou
  • Patent number: 10867931
    Abstract: Disclosed herein is a MOS transistor embedded substrate that includes first and second MOS transistors each having a source electrode formed on one surface and a drain electrode formed on other surface, and an insulation resin layer in which the first and second MOS transistors are embedded such that the source electrode of the first MOS transistor and the drain electrode of the second MOS transistor face a same direction and that the drain electrode of the first MOS transistor and the source electrode of the second MOS transistor face a same direction.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: December 15, 2020
    Assignee: TDK CORPORATION
    Inventors: Hironori Chiba, Toshiyuki Abe
  • Patent number: 10868008
    Abstract: Exemplary embodiments for an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: December 15, 2020
    Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Patent number: 10858757
    Abstract: An epitaxial substrate includes a single-crystal substrate of silicon carbide, and an epitaxial layer of silicon carbide disposed on the single-crystal substrate. The epitaxial layer includes a first epitaxial layer disposed on the single-crystal substrate, a second epitaxial layer disposed on the first epitaxial layer, and a third epitaxial layer disposed on the second epitaxial layer. The first epitaxial layer has a basal-plane-dislocation conversion rate of less than 95%. The second epitaxial layer has a basal-plane-dislocation conversion rate of more than 98%.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: December 8, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takanori Tanaka, Shigehisa Yamamoto, Yu Nakamura, Yasuhiro Kimura, Shuhei Nakata, Yoichiro Mitani
  • Patent number: 10861830
    Abstract: A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor devices. In an embodiment the package is an integrated fan out package. The link device may be bonded on either side of the package, and the package may optionally comprise through package vias. The link device may also be an integrated passive device that includes resistors, inductor, and capacitor components.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Chao-Yang Yeh, Ming-Tsun Lin, Hau Tao
  • Patent number: 10854562
    Abstract: A semiconductor device includes a semiconductor substrate having a chip region and an edge region, a plurality of connection structures provided in a lower insulating layer of the edge region and arranged at first intervals in a first direction, an upper insulating layer covering the connection structures, and a plurality of redistribution pads disposed on the upper insulating layer and connected to the connection structures, respectively. Each of the redistribution pads includes a pad portion provided on the chip region. The pad portions of the redistribution pads are spaced apart from the connection structures by a first distance in a second direction intersecting the first direction when viewed in a plan view.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Ho Shin, Bonhwi Gu, Hyekyeong Kweon, Sungjin Kim, Joodong Kim, Jaepil Lee, Dongwon Lim
  • Patent number: 10854578
    Abstract: Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 1, 2020
    Assignee: Invensas Corporation
    Inventor: Stephen Morein
  • Patent number: 10851232
    Abstract: The present application relates to an encapsulating composition and an organic electronic device comprising the same, and provides an encapsulating composition which can effectively block moisture or oxygen introduced into an organic electronic device from the outside to secure the lifetime of the organic electronic device, is possible to realize a top emission type organic electronic device, is applicable to an inkjet method, can provide a thin display and has excellent adhesion reliability.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 1, 2020
    Assignee: LG Chem, Ltd.
    Inventors: Kook Hyun Choi, Joon Hyung Kim, Yu Jin Woo, Mi Lim Yu
  • Patent number: 10838273
    Abstract: An array substrate, a repair method thereof, and a display device are disclosed. The array substrate includes: a substrate including a first electrode and a second electrode, wherein the first electrode and the second electrode are located in different layers, and a projection of the first electrode on the substrate does not overlap a projection of the second electrode on the substrate; a first conductive layer electrically connecting the first electrode and the second electrode through vias; and a repairing component configured to electrically connect the first electrode and the second electrode when an electrical connection between the first electrode and the second electrode fails.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: November 17, 2020
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Meng Liu, Shuo Tang, Peng Sun, Bin Feng
  • Patent number: 10840365
    Abstract: It is a purpose of the present invention to provide an insulated gate bipolar transistor device or the like that exhibits high performance and that is suitable for mass production. The insulated bipolar transistor device includes multiple trench structures including at least a trench gate, a first dummy trench, and a second dummy trench. The first dummy trench and the second dummy trench are configured as adjacent trenches. The trench gate is connected to a gate electrode layer. The first dummy trench and the second dummy trench are connected to an emitter electrode layer, and are not connected to the gate electrode layer. A first conductive source layer is also formed between the first dummy trench and the second dummy trench.
    Type: Grant
    Filed: December 9, 2017
    Date of Patent: November 17, 2020
    Assignees: Kyushu Institute of Technology, Mitsubishi Electric Corporation, Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Katsumi Satoh, Tomoko Matsudai